Chiplet Storage Architecture for Adaptable Host Interfaces

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Solution Overview

Problem

Current data storage systems face limitations in flexibility and compatibility with varying host device and memory media standards, requiring frequent changes in storage architecture when standards change, leading to inefficiencies and increased costs.

Innovation Solution

A chiplet-based storage architecture that includes a front-end chip for high-speed communication with host devices and multiple back-end chips for low-speed communication with memory devices, allowing for independent updates and replacements of chips to adapt to changing standards without altering the entire system, utilizing a daisy chain scheme for efficient data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a monolithic integrated circuit storage architecture is used, then the system has a simple structure, but it cannot adapt to changing host device and memory media standards

Engineering Contradiction:
Improveadaptability to changing standardsVSAvoidstorage architecture complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The storage architecture is divided into multiple independent chiplets (first chiplet, second chiplet, third chiplet, fourth chiplet) that can be selectively replaced. Each chiplet contains specific storage functions, allowing individual components to be updated or replaced without affecting the entire system, thus achieving adaptability while managing complexity through modular design.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If the entire storage system is redesigned when standards change, then full compatibility is achieved, but system redesign costs and time increase

Engineering Contradiction:
Improvecompatibility with new standardsVSAvoidsystem redesign time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The system is segmented into replaceable chiplets, enabling selective replacement of only the necessary components to support new standards rather than redesigning the entire system. This reduces redesign time and costs while maintaining full compatibility.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The storage architecture transitions from a static monolithic design to a dynamic modular system where chiplets can be selectively replaced and reconfigured. This dynamic capability allows the system to adapt to changing standards by swapping chiplets rather than undergoing complete redesign.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If a monolithic storage architecture is used, then manufacturing is simpler, but flexibility for different host devices and memory media is limited

Engineering Contradiction:
Improveflexibility for different standardsVSAvoidmanufacturing complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The storage system is manufactured as separate chiplets that can be independently produced and then assembled. This segmentation allows each chiplet to be optimized for specific functions and standards, while the modular nature simplifies the overall manufacturing process by enabling parallel production and selective assembly rather than manufacturing a complete monolithic system.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240427522A1Devices using chiplet based storage architectures
Publication Date: 2024.12.26 SK HYNIX INC
  • US20240427522A1 patent drawing
  • US20240427522A1 patent drawing
  • US20240427522A1 patent drawing

AI summary

A storage architecture includes a plurality of accelerator memory devices on a package substrate; a front-end chip located on the package substrate, and configured to perform communication with a host device; and a plurality of back-end chips configured to perform communication with the front-end chip on the package substrate and control at least a part of the plurality of accelerator memory devices, and coupled to each other in a daisy chain scheme.