Chiplet Storage Architecture Adaptability via Segmentation
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Solution Overview
Problem
Current data storage systems face limitations in flexibility and compatibility with varying host and memory device standards, particularly in systems-on-chip (SoC) configurations, where changes in interfacing standards require significant updates to the entire storage architecture.
Innovation Solution
A chiplet-based storage architecture with a front-end chip and multiple back-end chips, allowing for independent configuration and replacement of each chip, supports different communication protocols and standards through PCIe and CXL protocols, enabling adaptive data storage operations without needing to change the entire system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a monolithic integrated circuit or system-on-chip storage architecture is used, then the storage architecture can be implemented with a single skeleton integrated circuit, but the storage architecture becomes valid only for host devices and memory media of specific standards, reducing flexibility and adaptability
Solution Approach 1:
The storage architecture is divided into multiple independent chiplets (first chiplet, second chiplet, etc.) instead of a single monolithic integrated circuit. Each chiplet can be independently configured and replaced, allowing the system to adapt to different host devices and memory media standards without redesigning the entire storage architecture.
Solution Approach 2:
The interface circuit includes a protocol converter that can convert between different communication protocols (e.g., SATA, SAS, NVMe), enabling the same chiplet architecture to support multiple host device and memory media standards. This multi-functional capability allows a single chiplet design to serve various storage standards.
2Adaptability or versatility
If the entire storage architecture is updated to support new host or memory device standards, then compatibility with new standards is achieved, but significant system updates are required, increasing loss of time and complexity
Solution Approach 1:
The storage architecture uses independent chiplets that can be individually replaced or updated. When a new host or memory device standard is introduced, only the affected chiplet needs to be replaced, not the entire storage architecture, significantly reducing update time and system downtime.
Solution Approach 2:
The storage architecture is designed to be dynamic and reconfigurable, allowing chiplets to be added, removed, or replaced based on changing standards requirements. This dynamic capability enables the system to adapt to new standards without requiring a complete system redesign.
3Adaptability or versatility
If the entire storage architecture is updated to support new host or memory device standards, then compatibility with new standards is achieved, but extensive system updates are required, increasing device complexity
Solution Approach 1:
The storage architecture is segmented into independent chiplets with standardized interfaces. This segmentation allows targeted updates to only the necessary chiplets rather than the entire system, reducing the complexity of system updates while maintaining support for new standards.
Solution Approach 2:
The interface circuit acts as an intermediary between the chiplets and the host device/memory media, handling protocol conversions and compatibility mappings. This intermediary layer absorbs the complexity of standard transitions, allowing chiplets to remain simpler while the interface circuit manages the complexity of supporting multiple standards.
Data Source
AI summary
A data receiving circuit includes a forwarded fast clock domain configured to output data transmitted from a data transmitting circuit in synchronization with a forwarded fast clock signal, and a local clock domain configured to generate a synchronized fetch enable signal in synchronization with a local fast clock signal and output the data transmitted from the forwarded fast clock domain in synchronization with a local slow clock.