Semiconductor Chiplet Architecture for Switchless Pooled Memory

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Solution Overview

Problem

The current approach to building pooled memory systems using CXL switches between processors and memory modules introduces extra latency, power consumption, and cost, with latency being the most critical issue for system designers.

Innovation Solution

A mechanism is proposed to build pooled memory without using switches by employing a chiplet architecture with System-on-Chip (SoC) devices that directly connect to memory modules and utilize die-to-die or chip-to-chip interfaces for memory request forwarding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a CXL switch is used to build pooled memory between processors and memory modules, then memory pooling functionality is achieved, but latency increases by 300 to 450 ns

Engineering Contradiction:

Improvememory pooling functionalityVSAvoidaccess latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts and removes the CXL switch from the memory access path. Instead of routing all memory traffic through a centralized switch, the system directly connects processors to memory modules, eliminating the switch-induced latency of 300 to 450 ns while maintaining pooled memory functionality through direct peer-to-peer connections.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the monolithic CXL switch architecture into distributed direct connections between individual processors and memory modules. This segmentation allows each processor to access memory directly without going through a centralized switching fabric, thereby reducing latency while preserving the pooled memory capability across multiple processors.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If a CXL switch is used to build pooled memory, then memory sharing is enabled, but power consumption increases

Engineering Contradiction:

Improvememory sharing capabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent removes the power-consuming CXL switch from the system architecture. By enabling direct connections between processors and memory modules, the system achieves memory sharing functionality without the continuous power overhead of switch operation, thereby reducing overall power consumption while maintaining adaptability.

Inventive Principle:

Principle #2Taking out (Extraction)

3Adaptability or versatility

If a CXL switch is used to build pooled memory, then memory pooling is achieved, but system cost increases

Engineering Contradiction:

Improvepooled memory functionalityVSAvoidsystem cost

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent extracts the expensive CXL switch component from the system and replaces it with direct connections between processors and memory modules. This elimination of the switch reduces bill of materials cost and simplifies the manufacturing process while preserving the pooled memory functionality through a more cost-effective architecture.

Inventive Principle:

Principle #2Taking out (Extraction)

4Loss of time

If direct connections between processors and memory modules are used, then latency is reduced by 300 to 450 ns, but system complexity increases

Engineering Contradiction:

Improveaccess latencyVSAvoidconnection architecture

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent manages the complexity of direct connections by segmenting the system into discrete processor-memory pairs with dedicated interfaces. Each connection is simplified and standardized, allowing the overall system to achieve low latency through multiple simple direct links rather than one complex switched fabric, thereby distributing and managing complexity across modular units.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20250328479A1Semiconductor device and method of building a pooled memory without using switches

Publication Date: 2025.10.23 PRIMEMAS KOREA INC

AI summary

A semiconductor device includes a first processor configured to generate a first memory physical address and a first memory request; a second processor configured to generate a second memory physical address and a second memory request; a first system-on-chip physically connected to the first processor and configured to convert the first memory physical address into a first device address; a second system-on-chip physically connected to the second processor and the first system-on-chip and configured to convert the second memory physical address into a second device address; and a first memory and a second memory respectively and physically connected to the first system-on-chip and the second system-on-chip. The first system-on-chip and the second system-on-chip respectively forward the first memory request and the second memory request to one of a plurality of memories including the first memory and the second memory according to the first device address and the second device address.