Chiplet Throttle Level Bus for Dynamic Power and Thermal Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Chiplet-based systems face limitations in power and thermal management, which restrict their performance in varying electrical supply rail and thermal cooling environments, potentially reducing performance in intensive applications.
Innovation Solution
A chiplet system architecture with a throttle level bus and throttling logic circuitry that adjusts chiplet operation based on thermal and power excursions, using a throttle level bus to communicate throttle information among chiplets, allowing them to operate within safe thermal and power limits while maximizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If chiplet systems operate at maximum performance, then processing speed and computational capability are improved, but power consumption and thermal generation increase beyond safe limits
Solution Approach 1:
The patent implements dynamic power management by making the chiplet system's operational state changeable based on real-time conditions. The throttle level bus and throttling logic circuitry enable the system to transition between different performance states (full performance, throttled performance) according to power and thermal conditions, resolving the contradiction between maintaining high productivity and controlling power consumption.
Solution Approach 2:
The patent establishes a feedback mechanism where power consumption and thermal conditions are monitored, and this information is used to adjust the operational state of chiplets through the throttle level bus. The throttling logic receives feedback about power/thermal excursions and dynamically adjusts chiplet operation to maintain safe limits while maximizing performance when conditions permit.
2Productivity
If chiplet systems operate at maximum performance, then processing speed is improved, but thermal generation exceeds cooling capabilities
Solution Approach 1:
The system dynamically adjusts its thermal state by transitioning between full-performance mode and throttled mode based on real-time thermal monitoring. When thermal generation exceeds cooling capabilities, the throttle level bus signals chiplets to reduce operation, thereby dynamically controlling temperature while maintaining high speed when thermal conditions allow.
Solution Approach 2:
A thermal feedback loop is implemented where temperature sensors monitor thermal generation, and this information feeds back to the throttling logic which adjusts chiplet operation accordingly. This closed-loop control ensures thermal generation remains within cooling capabilities while maximizing processing speed when safe.
3Reliability
If power and thermal limits are strictly enforced, then system reliability is improved, but performance in intensive applications is reduced
Solution Approach 1:
Rather than enforcing static power and thermal limits, the system uses dynamic throttling that adjusts operational constraints in real-time based on actual conditions. This allows the system to maintain high reliability by preventing excursions beyond safe limits while maximizing performance during intensive applications when conditions permit, resolving the contradiction between reliability and performance.
Solution Approach 2:
The patent changes the operational parameters of chiplets dynamically by adjusting throttle levels based on real-time power and thermal measurements. This parameter adjustment allows the system to operate at high performance when conditions allow while maintaining reliability by reducing parameters (throttle level) when limits are approached, rather than enforcing fixed conservative limits.
Data Source
AI summary
A chiplet system comprises an interposer including interconnect and multiple chiplets arranged on the interposer and interconnected using the interconnect of the interposer. The multiple chiplets include a throttle level bus source chiplet including a throttle level bus drive interface configured to place a throttle level value onto the throttle level bus, and one or more throttle level bus receiver chiplets operatively coupled to the throttle level bus. Each chiplet of the multiple chiplets includes throttling logic circuitry configured to set a throttle level of a chiplet according to the throttle level value.