Chiplet Tree Topology for Scalable Neuromorphic Interconnects
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Solution Overview
Problem
Existing neuromorphic chip architectures face challenges with limited data transmission bandwidth and poor scalability, particularly in spiking neural networks (SNNs), due to monolithic processors and traditional interconnect methods like Bus, Crossbar, and Mesh, which result in low production yield, high latency, and increasing complexity.
Innovation Solution
A chiplet-based hierarchical tree topology architecture is introduced, organizing neuron processing entities (NPEs) and switches in a tree structure, with interposers and routers, enabling flexible and scalable data transmission through micro-bumps and configurable clocks, optimizing short-distance data communications and improving scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If monolithic processors are used to increase processing unit density and performance, then computing performance is improved, but manufacturing yield decreases and production cost increases due to larger die size
Solution Approach 1:
The patent divides the monolithic processor into multiple smaller chiplets, each containing a subset of processing units. These chiplets are manufactured separately on standard-sized wafers, ensuring high manufacturing yield, and then packaged together in an interposer to form a complete neuromorphic processing system. This segmentation allows the system to achieve high computing performance through increased processing unit density while maintaining high production yield through standardized wafer fabrication processes.
2Device complexity
If traditional Bus or Crossbar architectures are used for interconnect, then data transmission is simplified, but data transmission bandwidth is limited and scalability is poor
Solution Approach 1:
The patent transitions from traditional two-dimensional Bus or Crossbar interconnect topologies to a three-dimensional hierarchical interposer architecture. The interposer provides vertical stacking and multiple routing layers, enabling data to transmit through multiple dimensions simultaneously. This dimensional expansion dramatically increases data transmission bandwidth and allows the system to scale to larger numbers of processing units without the bandwidth limitations of flat interconnect topologies.
3Adaptability or versatility
If Mesh architecture is used to improve scalability, then system expansion is enabled, but data transmission latency increases and complexity grows
Solution Approach 1:
The patent implements a hierarchical interposer architecture where multiple chiplets are nested within a single interposer package. This nesting creates a compact, organized structure where data transmission paths are optimized and localized. Compared to a distributed Mesh architecture, the nested interposer structure reduces the average transmission distance and number of hops required for data to reach its destination, thereby reducing latency while maintaining scalability through modular chiplet addition.
4Quantity of substance
If larger die size is used to accommodate more processing units, then processing capacity increases, but manufacturing cost increases and production yield decreases
Solution Approach 1:
The patent segments the large-scale neuromorphic processing system into multiple smaller chiplets, each manufactured on standard-sized wafers using established fabrication processes. This segmentation enables high-volume production with consistent quality and lower cost per unit. The chiplets are then assembled in an interposer, achieving the equivalent of a large die with many processing units while avoiding the exponential cost and yield penalties associated with manufacturing single large-die processors.
Data Source
AI summary
This application describes chiplet-based neuromorphic systems, devices, and chips. An exemplary chiplet-based neuromorphic system may include: a plurality of neuron processing entities (NPE); a plurality of chiplets each comprising a plurality of switches and a group of NPEs from the plurality of NPEs; and a plurality of interposers each comprising a plurality of routers and a group of chiplets from the plurality of chiplets; wherein each of the plurality of switches within each chiplet connects to one or more of the group of NPEs, and the plurality of switches within the each chiplet are organized in a tree topology; wherein each of the plurality of routers within each interposers connects to one or more of the group of chiplets, and the plurality of routers within the each interposer are organized in a tree topology.