Chiplet Connecting Element for Vertical Memory Access
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Solution Overview
Problem
Conventional semiconductor packages face challenges in achieving low latency and high bandwidth memory access due to the use of long lateral conductive traces and multiple bridges, which increase cost, area overhead, and memory latency, especially as processor chip sizes increase.
Innovation Solution
Implementing a connecting element, such as a bridge interposer, to stitch processor chiplets together and enable vertical communication between processor chiplets and stacked memory units, using shorter vertical passthroughs to reduce latency and increase bandwidth without significant area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If long lateral conductive traces and multiple bridges are used to connect processor chiplets and memory units, then electrical connectivity between components is achieved, but memory latency increases and bandwidth is reduced
Solution Approach 1:
The patent transitions from lateral (2D) conductive traces to vertical (3D) conductive paths by stacking memory units above processor chiplets using through-silicon vias (TSVs). This dimensional change shortens the conductive path length, reducing memory latency while maintaining electrical connectivity between components.
Solution Approach 2:
The patent introduces an interposer as an intermediary component between processor chiplets and memory units. The interposer provides a platform for vertical integration, enabling shorter conductive paths through TSVs while facilitating electrical connectivity without requiring long lateral traces across the package.
2Reliability
If multiple bridges are used to connect processor chiplets and memory units, then electrical connectivity is achieved, but device complexity and cost increase
Solution Approach 1:
The patent merges the functions of multiple separate bridges into a single interposer structure. The interposer simultaneously connects multiple processor chiplets to multiple memory units through vertical TSV paths, reducing the total number of discrete bridge components needed while maintaining comprehensive electrical connectivity.
Solution Approach 2:
The interposer serves multiple functions: it acts as a mechanical support structure, provides electrical connectivity through TSVs, enables vertical stacking, and facilitates heat dissipation. This multi-functionality replaces the need for multiple specialized bridge components, reducing device complexity.
3Reliability
If long lateral conductive traces are used, then electrical connectivity between processor chiplets and memory units is achieved, but area overhead increases
Solution Approach 1:
The patent moves conductive paths from the lateral plane to the vertical dimension using TSVs and stacked architecture. This allows memory units to be positioned directly above processor chiplets, eliminating the need for long lateral traces and reducing the horizontal package footprint while maintaining electrical connectivity.
Data Source
AI summary
A structure is disclosed. The structure can include a first processor die, a second processor die, a first memory unit, and a connecting element. The second processor die can be laterally spaced from the first processor die. The first memory unit can be disposed vertically above the first processor die. The connecting element can be disposed vertically to the first processor die and the second processor die. The connecting element can include a conductor electrically connecting the first processor die and the second processor die.