Chipset Address Queues for Direct Memory Access
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Solution Overview
Problem
Conventional chipsets with multiple virtual channels are inefficient when serving peripherals with a single virtual channel, as they cannot fully utilize their hardware resources, leading to limited data access requests and reduced efficiency due to the need for serial buffering and detours through the CPU for snooping operations.
Innovation Solution
A method that utilizes two address queues to differentiate between snooping and non-snooping data access requests, allowing direct transmission to the system memory for non-snooping requests and buffering responses from the CPU and system memory in separate virtual channels to improve data access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the chipset combines buffers of multiple virtual channels in serial to serve a single virtual channel peripheral, then the buffer capacity is increased, but the data access efficiency deteriorates due to sequential processing
Solution Approach 1:
The patent segments the address queue into multiple independent address queues, one for each virtual channel. This allows parallel processing of data access requests from different virtual channels, eliminating the sequential processing bottleneck while maintaining increased buffer capacity through the combined queues.
2Productivity
If the chipset supports multiple virtual channels with independent buffers, then the data access throughput is improved, but the device complexity increases due to additional hardware requirements
Solution Approach 1:
The patent makes the address queue structure universal by designing it to accommodate multiple virtual channels simultaneously. The same address queue infrastructure serves both single virtual channel and multi-virtual channel operations, eliminating the need for separate dedicated hardware for each virtual channel while maintaining high throughput capability.
3Ease of operation
If the peripheral operates under a single virtual channel environment, then the ease of operation is maintained, but the hardware resource utilization deteriorates as the chipset's multiple VC capabilities remain idle
Solution Approach 1:
The patent enables the chipset to automatically adapt its address queue configuration based on the peripheral's virtual channel capability. When a single virtual channel peripheral is detected, the system self-configures to use one address queue for simplicity, while retaining the capability to utilize multiple queues when needed, thus achieving both ease of operation and hardware resource utilization.
Data Source
AI summary
Method and related apparatus for internal data accessing of a computer system. In a computer system, a peripheral can issue accessing requests for system memory space with or without snooping the central processing unit (CPU). While serving a peripheral of single virtual channel utilizing a chipset supporting multiple virtual channels, the present invention assigns accessing requests to different processing queues according to their snooping/non-snooping attributes, such that reading/non-snooping requests are directly routed to a system memory. Also responses from system memory and CPU are buffered in the chipset respectively by utilizing buffer resources of different virtual channels. And by applying accessing routing dispatch, data accessing efficiency can be increased.