Chipset Global Address Map for Heterogeneous NUMA Memory Access
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Solution Overview
Problem
Conventional computer architectures are not designed to support multiple heterogeneous processing units accessing each other's physical memory, limiting their ability to share resources effectively in multi-processor systems.
Innovation Solution
A method is implemented to generate a global address map by combining address maps from multiple processors, allowing each processor to access physical memory associated with other processors through a Non-Uniform Memory Access (NUMA) device, without modifying the processors, operating systems, or memory controllers, using a translation table to route memory access requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional computer architecture is used with single CPU design, then system simplicity is maintained, but multi-processor memory access capability is lost
Solution Approach 1:
The patent introduces a chipset as an intermediary component between processors and memory. The chipset includes a memory bridge that receives address maps from multiple processors and generates a global address map, enabling processors to access each other's local memory without direct processor-to-processor communication protocols. This mediator approach allows multi-processor memory access while keeping processors themselves unchanged and relatively simple.
Solution Approach 2:
The patent adds an address mapping dimension to the memory access system. Instead of direct physical address access, the system introduces a global address map that translates processor-specific addresses to physical memory addresses. This additional mapping layer enables cross-processor memory access while maintaining the original processor architecture.
2Adaptability or versatility
If homogeneous processors are used in multi-processor system, then system configuration is simplified, but hardware versatility is reduced
Solution Approach 1:
The chipset's memory bridge is designed to handle address maps from heterogeneous processors universally. It can receive and process address maps from different processor types and vendors, translating them all into a unified global address map. This universal handling capability allows the system to support processor heterogeneity without requiring processor-specific configuration logic.
Solution Approach 2:
Each processor provides its own address map to the chipset, and the chipset automatically combines these into a global address map. The system configures itself without external intervention - processors declare their memory regions, and the chipset autonomously creates the translation tables and routing logic, reducing configuration complexity despite hardware diversity.
3Adaptability or versatility
If processors are modified to support multi-processor access, then memory sharing capability is improved, but processor complexity and modification cost increase
Solution Approach 1:
The patent places the memory access coordination logic in the chipset rather than in the processors. The memory bridge in the chipset handles address translation and memory routing, allowing processors to access shared memory without any modification to their internal architecture or instruction sets. The processors remain simple, unaware of the multi-processor environment.
Solution Approach 2:
The patent separates the memory control functions from the processors and places them in the chipset. Address map generation, global address translation, and memory routing are segmented out into the chipset's memory bridge, leaving processors unchanged. This segmentation allows memory sharing capability to be added without modifying processor manufacturing.
Data Source
AI summary
A method for providing a first processor access to a memory associated with a second processor. The method includes receiving a first address map from the first processor that includes an MMIO aperture for a NUMA device, receiving a second address map from a second processor that includes MMIO apertures for hardware devices that the second processor is configured to access, and generating a global address map by combining the first and second address maps. The method further includes receiving an access request transmitted from the first processor to the NUMA device, generating a memory access request based on the first access request and a translation table that maps a first address associated with the first access request into a second address associated with the memory associated with the second processor, and routing the memory access request to the memory based on the global address map.