Communication Chipset Hardware Packet Filtering
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Solution Overview
Problem
Current communication systems are vulnerable to external attacks and high power consumption due to software-based packet processing, which can lead to processor malfunction and increased load, and are complex to integrate new processing modules across layers.
Innovation Solution
A communication chipset and apparatus that uses dedicated hardware logic to hierarchically build and filter packets across multiple layers, reducing processor load and power consumption, while automatically identifying processing modules and preventing unnecessary packet transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based packet processing is used, then flexible layer packet processing and easy adaptation to various communication protocols are enabled, but the apparatus is exposed to external attacks and processor malfunction risks
Solution Approach 1:
The patent divides the packet processing function into separate hardware modules for different OSI layers (physical layer, data link layer, network layer, transport layer). Each layer has its own dedicated hardware processing unit that operates independently, allowing flexible protocol support while eliminating software execution risks. The hardware modules are segmented to handle specific layer functions, preventing attack propagation across layers.
Solution Approach 2:
The patent replaces software-based packet processing with hardware-based processing logic. Instead of using a processor to execute software protocols, dedicated hardware circuits implement packet processing at each layer. This substitution eliminates the vulnerability window where software could be exploited by malicious packets, while hardware provides deterministic and secure processing.
2Adaptability or versatility
If software-based packet processing is used, then flexible packet processing is enabled, but processor load increases and may cause malfunction
Solution Approach 1:
The patent segments packet processing across multiple hardware modules, each handling specific OSI layers. The physical layer module processes physical signals, the data link layer module handles MAC addresses and frames, the network layer module processes IP addresses, and the transport layer module handles TCP/UDP. This segmentation distributes the processing load away from a single processor, enabling high-speed packet processing without overloading any single component.
Solution Approach 2:
The patent replaces processor-based software processing with dedicated hardware processing modules. Each hardware module is optimized for its specific layer's processing requirements, enabling parallel processing of packets at different layers. This hardware substitution eliminates the bottleneck of sequential software execution and significantly reduces processor load while maintaining processing flexibility.
3Productivity
If hardware logic is used for packet processing, then processor load is reduced, but the architecture becomes complex and difficult to integrate new processing modules
Solution Approach 1:
The patent segments the hardware architecture into modular layers, each with dedicated processing modules. The physical layer, data link layer, network layer, and transport layer are implemented as separate hardware modules that can be independently designed, tested, and integrated. This modular segmentation reduces overall architecture complexity by breaking down the complex packet processing function into manageable units with clear interfaces.
Solution Approach 2:
The patent designs universal interface protocols between hardware modules that enable flexible integration. Each layer's hardware module uses standardized interfaces to communicate with adjacent layers, allowing new processing modules to be integrated without redesigning the entire architecture. This universality principle enables the system to adapt to new communication protocols and requirements while maintaining architectural simplicity.
4Speed
If hardware logic processes packets without processor control, then processing speed increases, but power consumption increases
Solution Approach 1:
The patent implements preliminary packet filtering at lower layers (physical and data link layers) using hardware logic before packets reach higher layers. Unnecessary packets are filtered out early in the hierarchy, preventing them from consuming processing resources and power at subsequent layers. This preliminary action principle reduces overall power consumption by stopping packet processing early for irrelevant traffic.
Solution Approach 2:
The patent segments packet processing so that different hardware modules handle different aspects of packet processing. Simple filtering operations are performed at lower layers with minimal power consumption, while more complex processing occurs at higher layers only for relevant packets. This segmentation allows the system to process packets at high speed while minimizing total power consumption by avoiding unnecessary processing at all layers.
Data Source
AI summary
A communication chipset and a communication apparatus are disclosed. A register map establishes a communication channel with a plurality of apparatuses, a first data link module sends/receives physical layer data of a first type and processes a data link layer in accordance with the first type, and a second data link module sends/receives physical layer data of a second type and processing a data link layer in accordance with the second type. Further, a first processing module is connected to the first data link module and the second data link module and filters out data link data from the first data link module and the second data link module by using setup data of a plurality of communication channels stored in the register map.