Chipset Hardware Pin Control for Processor Data Bus Power Saving
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Solution Overview
Problem
Current power management methods in computer systems waste system resources and power as the LDT bus remains enabled even during power saving modes, leading to inefficient resource consumption.
Innovation Solution
A power saving method where the processor issues a halt instruction to enter a power saving state, the chipset disables the data bus by asserting a hardware pin, and only enables it when necessary for data transactions or interrupt requests, ensuring the bus is disabled when not in use.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the LDT bus is kept enabled during power saving mode, then data transmission capability is maintained, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the LDT bus enable/disable state changeable rather than fixed. The bus is dynamically disabled when the processor enters C1 state and dynamically enabled when data transmission is needed, allowing the system to adapt the bus state to current operational requirements and save power when not in use.
Solution Approach 2:
The patent changes the operational parameter of the LDT bus from a static enabled state to a dynamic state that can switch between enabled and disabled based on processor power state. This parameter change allows the bus to be disabled during power saving modes while maintaining the ability to enable it when needed for data communication.
2Adaptability or versatility
If the LDT_STOP pin is deasserted during power saving mode, then the LDT bus remains enabled, but system resources are wasted
Solution Approach 1:
The patent implements feedback by having the chipset monitor processor state and automatically control the LDT_STOP pin accordingly. When the processor enters C1 state, the chipset receives this information and automatically asserts the LDT_STOP pin to disable the bus, and deasserts it when data transmission is needed, creating a closed-loop control system that prevents resource waste.
3Use of energy by moving object
If the data bus is disabled during power saving state, then power consumption is reduced, but data transmission capability is lost
Solution Approach 1:
The patent resolves this contradiction by making the bus enable/disable state dynamic rather than static. The bus is disabled during power saving modes to save power, but can be quickly enabled when data transmission is needed, maintaining the capability to transmit data when required while minimizing power consumption during idle periods.
Data Source
AI summary
A power saving method is disclosed. A halt instruction is issued to enable transition from an operational state to a power saving state. The processor broadcasts a message to a chipset. The chipset receives the sleep message and enters a power saving state, and asserts a hardware pin to disable a data bus connecting the processor and the chipset. It is determined whether a request for data transaction required during the power saving process is issued to the chipset. If the request is issued to the chipset, the chipset deasserts the hardware pin to enable the data bus, transmits the request to the processor; and, when data transaction is complete, asserts the hardware pin by the chipset to disable the data bus.