Chipset Attached Memory Task Allocation for Power Reduction
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Solution Overview
Problem
Computer systems face challenges in efficiently managing power consumption and resource allocation as they handle increasingly complex tasks, leading to higher power usage and heat generation, especially with the integration of advanced graphics and processing demands in gaming and other applications.
Innovation Solution
The implementation of a system that allocates tasks between a main processing unit and a chipset attached processing unit, utilizing separate memory and power management to offload less power-intensive tasks to the chipset attached processing unit, allowing the main system to be power-gated and reducing overall power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If tasks are handled by the main processing unit and system memory, then computational capability and processing speed are improved, but power consumption and heat generation increase
Solution Approach 1:
The system is divided into two independent processing domains: the main processing unit with system memory for high-performance tasks, and the chipset attached processing unit with chipset attached memory for lower-power tasks. This segmentation allows selective activation of processing components based on task requirements, reducing overall power consumption while maintaining computational capability.
Solution Approach 2:
The chipset acts as an intermediary between the main processing unit and the chipset attached processing unit. It manages memory allocation, handles task offloading decisions, and coordinates data transfer between the two memory systems, enabling efficient power management without sacrificing system performance.
2Reliability
If the main system operates continuously to handle all tasks, then system functionality and response time are maintained, but power consumption and heat generation increase
Solution Approach 1:
The system dynamically adjusts its operational state by power-gating the main processing unit and system memory when tasks can be handled by the chipset attached processing unit. This dynamic power management maintains system functionality while reducing power consumption and heat generation during lower-demand operations.
Solution Approach 2:
The chipset attached processing unit with its dedicated memory serves itself independently for certain tasks, eliminating the need for the main system to remain active. This self-service capability allows the main system to be power-gated, reducing overall power consumption while maintaining essential system functionality.
3Use of energy by moving object
If chipset attached memory is used for task execution, then power consumption is reduced, but access speed and data rate may be limited
Solution Approach 1:
Different memory systems are optimized for different characteristics: system memory provides high-speed access for the main processing unit, while chipset attached memory provides adequate access speed with lower power consumption for the chipset attached processing unit. Each memory-processing combination operates in its optimal performance zone.
Solution Approach 2:
The chipset attached processing unit handles a subset of processing tasks that do not require the maximum data access rates of the system memory. By accepting partial action (handling only certain task types), the system achieves sufficient performance while reducing power consumption and heat generation.
Data Source
AI summary
Task allocation with chipset attached memory and additional processing unit is described. In accordance with the described techniques, a computing device includes a main system and one or more sub-systems which are coupled to the main system via a chipset link. The main system includes at least a processing unit and a system memory. The one or more sub-systems each include at least a chipset attached processing unit and a chipset attached memory. Contents of the system memory are transferable to the chipset attached memory of the sub-system via the chipset link to enable the chipset attached processing unit to perform the one or more tasks using the contents from the chipset attached memory.