Flexible Chirp Generator With Fine Phase Propagation
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Solution Overview
Problem
Conventional direct digital synthesis (DDS) chirp generators with parallel double accumulators require complex compensation schemes to change slope, frequency, or phase, making them inflexible and inefficient for generating N outputs per clock cycle.
Innovation Solution
A flexible chirp generator system that operates at 1/N the rate of the digital-to-analog converter (DAC) using a fine phase propagation block and coarse time recursion block, allowing for efficient control of phase, frequency, and slope changes, with a chain of fine phase propagation blocks and sine generators to produce sine wave output values separated by a fine time step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If parallel versions of double accumulator are employed to generate N outputs per clock cycle, then productivity is improved, but device complexity increases due to the need for complex compensation schemes
Solution Approach 1:
The system is divided into multiple independent parallel accumulators (first accumulator generating frequency, second accumulator generating phase) that operate simultaneously. Each accumulator processes one aspect of the chirp generation independently, eliminating the need for complex inter-accumulator compensation while achieving N outputs per clock cycle through parallel operation.
Solution Approach 2:
The frequency is pre-calculated and stored in the first accumulator before phase calculation begins in the second accumulator. By preparing the frequency values in advance through the first accumulator, the second accumulator can directly use these pre-computed values without requiring complex real-time compensation schemes.
2Ease of operation
If conventional double accumulator is used with clock rate same as DAC rate, then ease of operation is improved for command changes, but productivity decreases due to inability to generate N outputs per clock cycle efficiently
Solution Approach 1:
The system dynamically adjusts the operational rate by using parallel accumulators that can generate N outputs per clock cycle when high productivity is needed, while maintaining the ability to respond to command changes. The parallel architecture allows the system to operate at multiple effective rates without sacrificing command responsiveness.
Solution Approach 2:
The parallel accumulator system serves multiple functions simultaneously: it generates N outputs per clock cycle for high productivity while also maintaining the flexibility to respond to command changes. The same parallel structure that enables high-speed operation also provides the versatility needed for easy command implementation.
3Productivity
If parallel double accumulators are used to generate N outputs per clock cycle, then productivity is improved, but ease of operation worsens due to difficulty in implementing command changes
Solution Approach 1:
By separating frequency generation (first accumulator) from phase generation (second accumulator), the system allows independent control and modification of each function. Command changes can be applied to either accumulator independently, simplifying implementation while maintaining parallel operation for high productivity.
Data Source
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AI summary
A processing-efficient chirp generator that allows flexibility in controlling phase, frequency and slope, i.e., rate of change of frequency. In one embodiment, a fine phase propagation block (305) generates phase values in increments of the fine time step (m), each phase value also offset from other phase values by multiples of a coarse time step (N). The phase samples are realigned in time after conversion to digital-to-analog converter (DAC) values.