Chirp Linearity Detector Using Frequency Division and Mixing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Chirp radar systems rely on properly formed chirped pulses for performance, but lack a method to verify chirp characteristics in real-time, leading to potential reliability issues if assumptions about chirp formation are incorrect.
Innovation Solution
A chirp linearity detector is introduced, which includes a frequency divider, mixer, and analog-to-digital converter (ADC) to monitor the linearity of the phase-locked loop (PLL) generating the radio frequency (RF) chirp, scaling down the frequency ramp to a lower range for accurate tracking and avoiding harmonic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chirp radar operates under assumption that chirps are properly formed without verification, then system operation is maintained, but reliability deteriorates due to undetected chirp formation errors
Solution Approach 1:
The chirp radar system performs self-diagnosis by incorporating a monitoring mechanism that uses the VCO output signal itself to detect chirp linearity. The system monitors its own chirp formation by dividing the VCO output frequency and comparing it against expected linear frequency sweep characteristics, allowing the system to self-verify proper operation without external intervention.
Solution Approach 2:
The patent implements a feedback mechanism where the monitored chirp linearity information is fed back to the system controller. The controller receives the divided VCO output signal, processes it through the monitoring circuitry, and uses the resulting linearity assessment to determine whether chirp pulses are being formed correctly, enabling real-time verification and system reliability improvement.
2Measurement precision
If frequency divider ratio is increased to scale down frequency ramp to lower range, then measurement precision improves for tracking chirp linearity, but device complexity increases due to additional filtering requirements
Solution Approach 1:
The frequency division process is segmented into multiple stages with different division ratios. The patent applies a first frequency division to bring the VCO output to an intermediate range, then applies a second frequency division to achieve the final low frequency suitable for ADC sampling. This segmented approach allows precise measurement while managing the complexity of filtering at each stage.
Solution Approach 2:
The patent introduces an intermediary frequency stage between the high-frequency VCO output and the low-frequency ADC input. By using a first frequency divider to create an intermediate frequency and then a second frequency divider to reach the final low frequency, the system creates intermediate steps that simplify the filtering requirements compared to a single large frequency reduction step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables continuous monitoring of chirp linearity within an operating radar system, enhancing the reliability of chirp radar systems by ensuring adherence to expected frequency sweep characteristics, thereby improving performance and mitigating risks associated with incorrect chirp formation assumptions.
Implementation Method 1
divides a frequency of a phase-locked loop (PLL) output signal to produce a frequency divided output signal in a lower frequency range
Implementation Method 2
mixes the frequency divided output signal with a local oscillator signal to produce a mixer output signal
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a signal source frequency sampling circuit and a frequency sweep linearity measuring circuit. The signal source frequency sampling circuit comprises a programmable-divisor frequency divider circuit for receiving a signal source output signal from a signal source and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.