Chirp PLL Reset Circuit for Fast Frequency Return With Low Phase Noise
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Solution Overview
Problem
Frequency modulated continuous wave (FCMW) radar systems face challenges in achieving short reset times for frequency chirps, which require high phase locked loop (PLL) bandwidths, leading to increased phase noise, especially with large chirp bandwidths.
Innovation Solution
A phase locked loop design that includes a low pass filter with parallel capacitors and a voltage source connected during the reset phase to quickly equalize the control voltage, allowing for rapid frequency resetting without the need for high PLL bandwidths, thereby minimizing phase noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the PLL bandwidth is increased to achieve shorter reset times, then the reset time is reduced, but the phase noise increases
Solution Approach 1:
The patent applies dynamics by making the PLL bandwidth adjustable rather than fixed. The bandwidth is dynamically changed based on the operational phase: a first bandwidth is used during the acquisition phase for stable frequency tracking, and a second, higher bandwidth is used during the reset phase for rapid frequency transitions. This temporal differentiation resolves the contradiction by allowing the system to optimize for speed during resets while maintaining low noise during acquisition.
Solution Approach 2:
The patent implements periodic action by alternating between different bandwidth configurations in a cyclic manner corresponding to the chirp signal phases. The PLL bandwidth is periodically switched between the first bandwidth (during acquisition) and the second bandwidth (during reset), synchronizing with the periodic nature of the frequency chirp generation. This periodic adjustment allows the system to achieve short reset times when needed while maintaining low phase noise during the majority of the cycle.
2Measurement precision
If the chirp bandwidth is increased to improve radar resolution, then the measurement precision is improved, but the reset time must be reduced further, exacerbating the phase noise problem
Solution Approach 1:
The patent resolves this contradiction by dynamically adjusting the PLL bandwidth in response to the chirp bandwidth requirements. When a large chirp bandwidth is used for high resolution, the system automatically switches to a higher second bandwidth during the reset phase, enabling the VCO to rapidly traverse the larger frequency range without excessive phase noise. This dynamic adaptation allows the system to maintain high measurement precision while managing the increased reset time demands.
3Productivity
If the reset time is reduced to maximize acquisition time, then the productivity is improved, but the PLL bandwidth must be increased, leading to higher phase noise
Solution Approach 1:
The patent applies periodic action by implementing a cyclic switching mechanism that alternates between low-bandwidth operation during acquisition phases and high-bandwidth operation during reset phases. This periodic bandwidth adjustment allows the system to maximize acquisition time efficiency by keeping resets brief and infrequent, while maintaining low phase noise during the extended acquisition periods. The timing controller coordinates these periodic bandwidth changes to align with the chirp signal generation cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a short reset time for FCMW radar systems, optimizing dynamic range and reducing power consumption while minimizing phase noise, allowing for improved radar system performance.
Implementation Method 1
a voltage source configured to generate an initial control voltage, wherein the voltage source is switchably connected to a node between a first capacitor of the plurality of capacitors and the common voltage line
Implementation Method 2
the voltage source is connected between the first capacitor and the common voltage line during a chirp reset mode defined by the reset pulse such that the voltage at the node is substantially equalised to the initial control voltage
Implementation Method 3
a voltage controlled oscillator configured to generate the frequency chirp at an output in response to receiving the control voltage
Implementation Method 4
a feedback path connecting the output of the voltage controlled oscillator to a second input of the phase frequency detector, the feedback path comprising a frequency divider
Data Source
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AI summary
A phase locked loop for generating a frequency chirp is disclosed. The phase locked loop comprises a phase frequency detector (301) configured to receive a reference frequency signal at a first input (304a), a low pass filter (302) configured to receive a current from the phase frequency detector (301) at a filter input, and to output a control voltage, a voltage controlled oscillator (303) configured to generate the frequency chirp at an output in response to receiving the control voltage, a feedback path (305) connecting the output of the voltage controlled oscillator (303) to a second input of the phase frequency detector (301), the feedback path comprising a frequency divider (306); and a timing module (307) configured to generate a reset pulse. The low pass filter (302) comprises a plurality of capacitors (307a-c) connected in parallel between the filter input and a common voltage line (313); and a voltage source (308) configured to generate an initial control voltage. The voltage source (308) is switchably connected to a node (n1) between a first capacitor (307a) of the plurality of capacitors and the common voltage line (313), and is connected to the node (n1) during a chirp reset mode defined by the reset pulse such that the voltage at the node (n1) is substantially equalised to the initial control voltage.