Chlorosilane Silicon Deposition on III-V Substrates

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Solution Overview

Problem

Current silicon deposition methods, such as Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD), face challenges in achieving self-limiting and saturating growth on non-silicon surfaces, particularly at lower temperatures, and are not compatible with three-dimensional device processing like finFETs on large semiconductor wafers.

Innovation Solution

A method involving cycling dosing of chlorosilane precursors on III-V surfaces between 300° C. and 500° C. to form a silicon layer, followed by desorbing chlorine with atomic hydrogen, allowing for self-limiting and saturating silicon deposition, including the formation of silicon multilayers on various non-silicon substrates like InxGa1−xAs, InxGa1−xSb, InxGa1−xN, and SiGe, ensuring atomically ordered growth.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If sub 400°C ALD process is used for growing monolayers of Si on clean surfaces, then silicon deposition is achieved at lower temperature, but the process is slow with each ALD cycle taking several minutes and HCl desorption is slow below 400°C

Engineering Contradiction:
Improvesubstrate temperatureVSAvoiddeposition speed
Core Design Contradiction:
TemperatureVSProductivity

Solution Approach 1:

The patent changes the chemical parameters of the deposition process by using alternative precursors (TMCS and SiH4) and modifying the reaction mechanism to enable faster deposition rates at lower temperatures through a self-limiting surface reaction mechanism

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the conventional ALD mechanism with a new chemical reaction pathway that uses methyltrichlorosilane and silane to form silicon monolayers through a different chemical mechanism, achieving both low temperature operation and high deposition speed

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Manufacturing precision

If conventional ALD or CVD processes are used for silicon deposition on non-silicon surfaces, then silicon layers can be formed, but the processes are not self-limiting and saturating

Engineering Contradiction:
Improveself-limiting growth controlVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent implements a self-limiting deposition process where the surface reaction automatically saturates when all available surface sites are occupied by silicon atoms, eliminating the need for complex feedback control mechanisms and enabling precise monolayer formation

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent uses periodic pulsing of precursors (TMCS followed by SiH4) to achieve controlled, self-limiting deposition where each pulse cycle deposits a precise amount of silicon that automatically terminates when surface sites are saturated

Inventive Principle:
Principle #19Periodic action

3Reliability

If PVD deposition of silicon is used for passivation of III-V surfaces, then silicon can be deposited, but a silicon multilayer is required and the process is not compatible with processing of three dimensional devices such as finFETs on large semiconductor wafers

Engineering Contradiction:
Improvesurface passivation qualityVSAvoidmultilayer structure requirement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the essential function of silicon deposition for surface passivation and achieves it through a single-layer CVD process that provides adequate passivation without requiring complex multilayer structures, thereby simplifying the device fabrication process

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables self-limiting and saturating silicon deposition on non-silicon surfaces, producing atomically ordered silicon layers that are thermally stable and compatible with complex semiconductor device fabrication, including finFETs, while preventing contamination and oxidation.

Implementation Method 1

cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300° C. and 500° C. to form a first layer

Methodology Applied
Scientific EffectChemical Vapor Deposition: Chemical Vapour Deposition

Implementation Method 2

desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer

Methodology Applied
Scientific EffectDesorption: Desorption

Data Source

PatentUS10373824B2CVD silicon monolayer formation method and gate oxide ALD formation on semiconductor materials
Publication Date: 2019.08.06 APPLIED MATERIALS INC
  • US10373824B2 patent drawing
  • US10373824B2 patent drawing
  • US10373824B2 patent drawing

AI summary

Methods for depositing silicon include cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300° C. and 500° C. to form a first layer. Methods may include desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer. Methods may include forming a silicon multilayer on the second layer by cycling dosing between 1 and 100 cycles of one or more second chlorosilane precursors and atomic hydrogen at a temperature between 300° C. and 500° C. A layered composition includes a first layer selected from the group consisting of InxGa1−xAs, InxGa1−xSb, InxGa1−xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.