Choice Network Placement for Circuit Design Implementation
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Solution Overview
Problem
Existing implementation flows for integrated circuits (ICs) face inefficiencies in determining the quality of physical circuit implementations, as metrics used for logical networks are often unreliable indicators of the resulting physical implementation quality, leading to suboptimal results and lengthy randomization tool execution times.
Innovation Solution
The implementation flow utilizes choice networks, where multiple synthesis techniques optimize circuit designs with different objectives, and the resulting choice networks are processed through analytical placement to select the most suitable network for further processing, reducing reliance on unreliable metrics and improving execution efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple synthesis techniques are applied to generate alternate implementations, then the quality of physical circuit implementation is improved, but the execution time increases significantly
Solution Approach 1:
The patent applies preliminary action by performing analytical placement early in the flow on choice networks generated by multiple synthesis techniques. This preliminary placement information is then used to guide subsequent detailed placement and routing, avoiding the need to perform complete place-and-route for each alternate implementation. The analytical placement provides a foundation that accelerates the overall process while still enabling quality comparison of different synthesis approaches.
Solution Approach 2:
The patent segments the implementation flow into distinct phases: generating choice networks from multiple synthesis techniques, performing analytical placement on these choice networks, and then using the results to guide detailed placement and routing. This segmentation allows the computationally intensive analytical placement to be performed once on simplified representations rather than repeatedly on full implementations, reducing overall execution time while maintaining the ability to compare different synthesis approaches.
2Ease of operation
If metrics are used to evaluate logical network quality, then the evaluation process is simplified, but the reliability of physical implementation quality assessment deteriorates
Solution Approach 1:
The patent introduces analytical placement as an intermediary between logical network generation and physical implementation. Instead of directly using simple metrics on logical networks or performing complete place-and-route for evaluation, the analytical placement serves as a mediator that provides more reliable physical implementation estimates. This intermediary step bridges the gap between simple evaluation and accurate physical quality assessment, providing reliable guidance without requiring full implementation for each evaluation.
Data Source
AI summary
A computer-implemented method of implementing a circuit design that includes an initial network within a programmable logic device can include generating a first choice network from the circuit design according to a first synthesis technique and determining a placement for the first choice network. At least a second choice network can be generated from the first choice network according to a second synthesis technique. A placement for the second choice network can be determined. The placement for the first choice network can be compared with the placement for the second choice network. A placement and corresponding choice network can be selected according to the comparison, and output.