Cholesky Decomposition Circuit for High-Throughput Matrix Processing
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Solution Overview
Problem
Current matrix decomposition methods, particularly Cholesky decomposition, face limitations in high-throughput applications such as 3GPP-LTE wireless communication due to the need for frequent matrix decomposition operations, which can hinder performance in high-speed processes.
Innovation Solution
A circuit and method for calculating Cholesky decomposition are developed, utilizing a control circuit to iteratively distribute values through a series of processing circuits, enabling efficient generation of inverse square roots, products, and differences to achieve the decomposition, specifically designed for high-throughput implementations using a single-cell architecture and systolic array architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional matrix decomposition methods are used, then the decomposition can be performed, but the processing speed and throughput are limited in high-speed applications
Solution Approach 1:
The patent divides the Cholesky decomposition process into multiple independent computational stages: inverse square root calculation, multiplication, and subtraction operations. Each stage is handled by dedicated circuit blocks that process matrix elements in parallel, enabling high-throughput decomposition suitable for 3GPP-LTE wireless communication applications.
Solution Approach 2:
The patent transitions from sequential processing to parallel processing by introducing multiple input and output ports that operate simultaneously. The circuit architecture enables concurrent execution of decomposition operations across different matrix elements, significantly improving throughput for high-speed communication applications.
2Productivity
If frequent matrix decomposition operations are performed, then the decomposition can be applied to many data points, but the computational complexity and processing time increase
Solution Approach 1:
The patent implements continuous pipeline processing where matrix decomposition operations are performed continuously without idle time. The control circuit coordinates multiple circuit blocks to operate in an overlapping fashion, with each block processing different matrix elements simultaneously, maintaining continuous computational throughput for frequent decomposition operations.
Solution Approach 2:
The patent pre-computes and stores inverse square root values and intermediate products in memory structures during earlier stages of the decomposition process. These pre-computed values are readily available for subsequent multiplication and subtraction operations, reducing the overall processing time for frequent decomposition tasks.
3Device complexity
If a single-cell architecture is used, then the device complexity is reduced, but the computational capability may be limited
Solution Approach 1:
The patent designs a universal single-cell architecture where one circuit block can perform multiple functions by switching between different operational modes. The same basic circuit structure handles inverse square root calculations, multiplications, and subtractions through controlled signal routing and timing, reducing device complexity while maintaining full computational capability for Cholesky decomposition.
Data Source
AI summary
Approaches for Cholesky decomposition of a matrix are described. A first circuit is configured to generate an inverse square root of an input value. A second circuit is configured to generate a product of a value output by the first circuit and provided at a first input and a value provided at a second input. A third circuit is configured to generate a difference between a value provided at the first input and a value provided at the second input of the third circuit. The first input of the third circuit is coupled to the output of the second circuit. A control circuit is configured to iteratively distribute a plurality of values of the matrix and the outputs of the first, second, and third circuits to the inputs of the first, second, and third circuits such that the Cholesky decomposition of the matrix is output by the third circuit.