Chopped ADC Signal Chain With Dual Track-and-Hold for Low Drift
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Solution Overview
Problem
Existing ADC circuits face a tradeoff between sample rate, conversion accuracy, and power consumption, with high power consumption during idling times due to noise introduction and longer conversion times without chopping.
Innovation Solution
Implementing chop circuits in combination with multiple track-and-hold circuits to alternate signal polarities during sampling periods, allowing simultaneous acquisition and conversion of input signal polarities, and operating T/H circuits and ADC at higher frequencies to reduce idling time and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If ADC circuit operates continuously to maintain readiness for signal conversion, then conversion speed is improved, but power consumption increases during idling time
Solution Approach 1:
The ADC circuit is put into idle mode during periods when no signal is present and activated only when a signal needs to be converted. This periodic operation allows the circuit to consume minimal power during idle time while maintaining the ability to perform rapid conversion when needed, resolving the contradiction between continuous operation speed and power consumption.
2Measurement precision
If chopping is used to reduce noise and improve accuracy, then measurement precision is improved, but conversion time increases due to alternating polarities
Solution Approach 1:
The signal is pre-chopped into alternating polarities before being fed to the ADC converter. This preliminary chopping action prepares the signal in advance, allowing the ADC to process it more efficiently. By performing the chopping operation beforehand and using a dedicated chopping circuit, the conversion process itself can proceed faster while still benefiting from the noise-reduction effects of polarity alternation.
Data Source
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AI summary
Described herein are techniques that improve efficiency of analog-to-digital conversion circuits by reducing idling time, during which the ADC circuit is not converting an analog signal to a digital representation, which reduces associated power consumption from keeping the ADC circuit running during idling time. In some embodiments, chop circuits may be used in combination with a plurality of track-and- hold circuits to acquire one polarity of an input signal and convert another polarity of the input signal during a same sampling period. A chop circuit may be configured to alternate between generating a first polarity of the input signal and a second polarity of the input signal. A first T/H circuit may be configured to acquire one polarity of the input signal from the chop circuit while a second T/H circuit provides another polarity of the input signal, previously acquired from the chop circuit, to an ADC for conversion.