Chopped Comparator Relaxation Oscillator for Stable Frequency

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Solution Overview

Problem

Relaxation oscillators in industrial applications face limitations in output frequency stability due to the stability of reference elements and non-idealities of the comparator stage, leading to potential lock-up and catastrophic failures.

Innovation Solution

A simplified relaxation oscillator circuit is designed with a chopped comparator unit comprising a switching unit, sensing comparator, replica comparator, and combinatorial logic, which alternates clock signals to reduce lock-up possibilities and improve signal integrity by retaining comparator roles throughout operation and providing propagation delay information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a complex chopped comparator scheme and complex logic unit are used, then measurement precision and reliability can be improved by canceling offset voltage and propagation delay, but device complexity increases and lock-up risk occurs

Engineering Contradiction:
Improveoutput frequency stabilityVSAvoidcomparator and logic unit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and separates the offset voltage cancellation function and propagation delay measurement function into distinct circuit modules. The offset cancellation is achieved by separating the comparator into two phases: a first phase for offset measurement and a second phase for normal operation. The propagation delay is measured by extracting timing information from the comparator output and processing it through dedicated logic circuits, rather than attempting to eliminate it through complex comparator design.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies preliminary action by measuring and compensating for offset voltage before the main oscillation operation begins. The circuit performs an initial calibration phase where the offset voltage is measured and stored, then this information is used to compensate during normal operation. Similarly, propagation delay is measured in advance and used to adjust timing-critical operations.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If reference elements stability is improved, then output frequency stability is enhanced, but manufacturing cost and device complexity increase

Engineering Contradiction:
Improveoutput frequency stabilityVSAvoidreference element complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms where the actual comparator output timing information is fed back to adjust the effective reference timing. The propagation delay measurement is fed back to the logic unit, which uses this information to compensate for timing errors in the oscillation cycle. This feedback approach allows the use of simpler reference elements while achieving high stability through dynamic correction.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If comparator propagation delay is canceled, then output frequency stability is improved, but device complexity and manufacturing difficulty increase

Engineering Contradiction:
Improvefrequency stabilityVSAvoidcircuit manufacturing simplicity
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent uses copying by creating a replica of the comparator's timing behavior in the logic unit. Instead of attempting to build a perfectly zero-delay comparator, the circuit measures the actual delay of the existing comparator and creates a corresponding delay model in the logic unit. This model is then used to compensate for the delay effects, achieving stability without requiring ultra-precise comparator manufacturing.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS12184288B2Oscillator circuit
Publication Date: 2024.12.31 AMS INTERNATIONAL AG
  • US12184288B2 patent drawing
  • US12184288B2 patent drawing
  • US12184288B2 patent drawing

AI summary

An oscillator circuit includes a first integrator unit to charge a first capacitor at a first integration node, a second integrator unit to charge a second capacitor at a second integration node, a chopped comparator unit and a logic unit. The chopped comparator unit includes a switching unit, a sensing comparator and a replica comparator. The switching unit is configured to couple the first integration node, the second integration node and a reference voltage VREF to the sensing comparator and the replica comparator, depending upon a phase determined by a first input clock signal C1 and a second input clock signal C2, which have opposite phases. The logic unit is configured to generate signals C1, C2, D1, D2, E1, E2 for controlling each integrator unit.