Chopped Reference DAC for Sigma-Delta ADC Offset Cancellation
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Solution Overview
Problem
High-resolution analog-to-digital converters face challenges in reducing 1/f noise and DC offset from voltage reference sources, which affect signal-to-noise ratio and require complex calibration and trimming.
Innovation Solution
A five-level digital-to-analog converter using a chopped reference voltage generator and a switched capacitor stage with a switching sequencer that generates switching patterns with opposite polarities to cancel out offset and reduce 1/f noise, achieving inherent linearity and noise reduction without the need for additional calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage reference source is used in high-resolution ADC, then the converter can operate, but 1/f noise and DC offset are introduced that degrade signal-to-noise ratio
Solution Approach 1:
The patent applies chopper stabilization by periodically switching the voltage reference between two states (chopped reference voltage Vref_chop) to modulate the DC offset and 1/f noise to higher frequencies where they can be filtered out by the sigma-delta modulator's inherent noise shaping and digital filtering
Solution Approach 2:
The patent converts the harmful DC offset and 1/f noise from the voltage reference into a beneficial form by using chopper modulation to shift these errors to high frequencies, where they are then naturally rejected by the oversampled sigma-delta architecture's digital decimation filter
2Measurement precision
If complex calibration and trimming are applied to reduce DC offset, then accuracy improves, but device complexity increases
Solution Approach 1:
The patent implements self-calibration through the chopper stabilization mechanism, where the system automatically cancels its own DC offset and 1/f noise without requiring external calibration equipment or manual trimming procedures - the chopper modulator and sigma-delta filter work together to inherently reject these errors
3Reliability
If oversampling is increased to reduce thermal noise, then signal-to-noise ratio improves, but 1/f noise and DC offset remain unaffected
Solution Approach 1:
The patent combines oversampling with chopper modulation, where the periodic switching converts the stationary 1/f noise and DC offset into time-varying signals at the chopper frequency, allowing the oversampled architecture to filter these modulated errors along with thermal noise through digital decimation
4Measurement precision
If a chopper stabilized voltage reference is used to reduce DC offset, then offset error decreases, but high-frequency modulation components are introduced that require additional filtering
Solution Approach 1:
The patent merges the chopper stabilized reference with the sigma-delta modulator architecture, where the high-frequency chopping components are naturally filtered by the modulator's built-in noise shaping and digital decimation filter, eliminating the need for separate analog low-pass filters
Data Source
AI summary
A multi-bit digital-to-analog converter has a reference voltage generator generating a reference voltage with an offset voltage; a switched capacitor stage for generating a plurality of output voltages; and a switching sequencer controlling the switched capacitor stage operable to generate switching patterns for each output voltages, wherein each pattern has a charge phase and a transfer phase, and wherein for at least one output voltage the switching sequencer provides two switching patterns wherein each switching pattern contributes an offset of opposite polarity.