Chopper Amplifier Clock Reset for Common-Mode Phase Synchronization
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Solution Overview
Problem
Instrumentation amplifiers face challenges in maintaining synchronization of clock signals due to differences in common-mode voltages between input and feedback ports, leading to desynchronization and errors in offset voltage correction and flicker noise reduction.
Innovation Solution
An apparatus and method that include a correction circuit to determine common mode voltages, manipulate clock signals based on these voltages, and reset them if out of phase, ensuring synchronization and accurate operation of modulator and demodulator circuits in chopper amplifiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If chopping is applied to both input and feedback transconductors to correct offset voltage and reduce flicker noise, then measurement precision is improved, but device complexity increases due to the need for multiple modulator circuits and clock signal management
Solution Approach 1:
The patent implements a feedback mechanism where the output of the feedback transconductor is fed back through a feedback modulator to the summing node. This feedback loop enables continuous correction of offset voltage and flicker noise by comparing the actual output with the desired output and adjusting accordingly, thereby improving measurement precision while managing complexity through systematic signal routing
Solution Approach 2:
The patent employs periodic chopping action using clock signals to modulate both input and feedback transconductors. By periodically switching the transconductors on and off at high frequency, offset voltage and flicker noise are up-converted to frequencies outside the signal bandwidth, improving measurement precision. The periodic nature allows synchronization between multiple modulator circuits through shared clock signals
2Adaptability or versatility
If clock signal amplitudes are made to track common-mode voltages to improve adaptability, then adaptability is improved, but reliability deteriorates due to potential desynchronization and phase errors
Solution Approach 1:
The patent uses common-mode voltage tracking to adjust clock signal amplitudes, ensuring that each modulator circuit operates at the appropriate voltage level for its specific common-mode condition. This equipotential approach allows the system to adapt to different common-mode voltages at input and feedback ports while maintaining proper signal levels, improving adaptability without causing desynchronization
Solution Approach 2:
The patent introduces common-mode voltage sensing circuits as intermediaries that monitor the common-mode levels at different ports and use this information to adjust clock signal amplitudes. These sensing circuits act as mediators between the variable common-mode conditions and the clock signal generation, enabling adaptive amplitude adjustment while maintaining synchronization through centralized control
3Adaptability or versatility
If multiple modulator circuits operate independently with CM-voltage-dependent clocks to enhance adaptability, then adaptability is improved, but measurement precision worsens due to phase desynchronization
Solution Approach 1:
The patent segments the modulator circuits into independent input and feedback modulators, each capable of operating with its own common-mode voltage conditions. This segmentation allows independent adaptation to local conditions while maintaining overall system functionality. Each modulator can be optimized for its specific port's common-mode voltage without affecting the other's adaptability
Solution Approach 2:
The patent implements a universal clock distribution system that provides synchronized clock signals to multiple modulator circuits. The clock system is designed to be multi-functional, serving both input and feedback modulators while maintaining phase coherence. This universal approach ensures that all modulators operate in sync, preventing phase desynchronization errors while allowing each to adapt to its common-mode voltage
Data Source
AI summary
An apparatus includes an amplifier, an input port, a first modulator circuit connected to the input port, and a correction circuit. The correction circuit is configured to determine a common mode voltage of the input port and receive a first clock signal. The correction circuit is further configured to manipulate, based at least in part upon the common mode voltage of the input port, the first clock signal to generate a second clock signal. The second clock signal is produced for the first modulator circuit. The correction circuit is further configured to determine whether the second clock signal is out of phase with a third clock signal, and, based upon a determination that the second clock signal is out of phase with the third clock signal, reset the second clock signal.