Chopper Signal Generation Circuit for Ripple-Cancelled Clock Stability
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Solution Overview
Problem
Existing frequency locked loop circuits are prone to noise interference and instability due to internal noise generation, which affects the accuracy and stability of clock signals.
Innovation Solution
A signal generation circuit incorporating a first chopper, operational transconductance amplifier, and a ripple reduction loop circuit with a third chopper and operational amplifier to convert ripple into a direct current offset signal, which is used to compensate for offset voltages in the operational transconductance amplifier, ensuring stability of the reference clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a frequency locked loop circuit is used to prevent clock signal interference, then noise resistance is improved, but internal noise generation increases
Solution Approach 1:
The patent converts the harmful internal noise (ripple) generated by the frequency locked loop circuit into a beneficial compensation signal. The ripple reduction loop circuit detects the ripple at the output node, processes it through a third chopper and operational amplifier to generate a compensation signal, and feeds it back to cancel the original ripple, thereby transforming the harmful noise into a useful corrective element.
Solution Approach 2:
The patent implements a feedback mechanism through the ripple reduction loop circuit that continuously monitors the output signal for ripple components and generates compensating signals fed back to the operational transconductance amplifier. This closed-loop feedback system dynamically counteracts the internal noise generation, allowing the circuit to maintain noise resistance while minimizing self-generated interference.
2Reliability
If the frequency locked loop circuit is adjusted to ensure accuracy, then clock signal stability is improved, but circuit complexity increases
Solution Approach 1:
The patent segments the frequency locked loop circuit into distinct functional modules: the main signal generation path with the operational transconductance amplifier, and a separate ripple reduction loop circuit. This segmentation allows each module to be optimized independently - the main circuit focuses on signal generation while the dedicated ripple reduction loop handles noise cancellation, thereby improving stability without excessively complicating the overall circuit design.
Data Source
AI summary
A signal generation circuit comprising a first chopper, an operational transconductance amplifier, a second chopper and a ripple reduction loop circuit. The operational transconductance amplifier is coupled to receive a differential input signal, and the differential input signal is processed into an output signal at an output node by the operational transconductance amplifier and the second chopper. The ripple reduction loop circuit is coupled between the output node and a compensation node of the operational transconductance amplifier. The ripple reduction loop circuit comprises a third chopper and an operational amplifier. The third chopper is configured to convert a ripple in the output signal into a direct current offset signal. The operational amplifier is configured to convert the direct current offset signal into a compensation signal. The compensation signal is configured to input to the compensation node of the current mirror circuit.