Multi-Stage Chopper Switch Circuit for Low Input Bias Current
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Chopper-stabilized operational amplifiers face a significant challenge with increased input bias current due to charge injection and clock feed-through, which is proportional to the chopping clock frequency and voltage level, and is difficult to reduce without increasing ripple voltages or enlarging notch filter capacitors.
Innovation Solution
The implementation of a chopper-stabilized circuit with pre-chopping, main chopping, and post-chopping stages operating at different frequencies, where the pre-chopping frequency is a sub-harmonic of the main frequency, combined with a switched capacitor notch filter that operates synchronously with the chopping signals to reduce ripple voltages, effectively minimizing input bias current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the chopping clock frequency is reduced, then input bias current is reduced, but ripple voltage increases requiring larger filter capacitors
Solution Approach 1:
The patent divides the single chopping operation into multiple sequential chopping stages, each operating at different frequencies. The first chopping stage operates at a lower frequency to minimize charge injection and input bias current, while subsequent stages operate at higher frequencies to maintain low ripple voltage. This segmentation allows each stage to be optimized for its specific function without compromising the other.
Solution Approach 2:
The patent employs periodic chopping actions at multiple frequencies rather than a single continuous frequency. By using periodic chopping with carefully selected frequency ratios, the system achieves both low input bias current (from lower frequency stages) and low ripple voltage (from higher frequency stages), with the periodic nature allowing synchronization of the different frequency components.
2Object-generated harmful factors
If the chopping clock voltage level is reduced, then charge injection is reduced, but chopping effectiveness decreases
Solution Approach 1:
The patent segments the chopping function across multiple stages, allowing the first stage to use lower voltage levels for reduced charge injection, while subsequent stages use higher voltage levels to maintain effective chopping. This segmentation enables voltage optimization at each stage independently.
Solution Approach 2:
The patent introduces intermediate chopping stages that act as mediators between the input signal and the final output. These intermediate stages can operate at optimized voltage levels appropriate for their specific function, with the first stage using lower voltages to reduce charge injection and later stages using higher voltages to ensure effective signal processing.
3Object-affected harmful factors
If notch filter capacitor size is increased, then ripple voltage is reduced, but circuit complexity and die size increase
Solution Approach 1:
The patent segments the ripple filtering function across multiple chopping stages rather than relying on a single large capacitor in one stage. Each stage contributes to ripple reduction, allowing the use of smaller capacitors at each stage while achieving the same overall ripple suppression effect, thereby reducing total circuit complexity and die size.
Solution Approach 2:
The patent maintains continuous ripple suppression through multiple sequential chopping stages, each contributing to the overall filtering effect. This continuous multi-stage approach replaces the need for large discrete filtering components with a distributed filtering system that achieves the same result with smaller, more manageable components.
Data Source
AI summary
A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.


