Chronos Links ASIC Interconnect Protocol
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Solution Overview
Problem
Conventional ASIC design is labor-intensive and power-consuming due to the need for manual intervention in clock alignment and timing closure, which is susceptible to process, voltage, and temperature variations, and requires numerous buffers for clock signal distribution.
Innovation Solution
The implementation of Chronos Links, an on-chip and off-chip interconnect communication protocol that uses gaskets and channel repeaters to replace traditional links, enabling simplified floorplanning, clock tree synthesis, and timing closure, while allowing for independent clock references and temporal compression to reduce overhead and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock tree synthesis with numerous buffers is used to achieve timing closure, then clock signal distribution across the chip is improved, but power consumption increases significantly and device complexity increases
Solution Approach 1:
The patent extracts and removes the clock tree synthesis step entirely from the design flow. By using independent clock references at each IP block interface, the complex buffer-based clock distribution network is eliminated, achieving timing closure without the power-consuming infrastructure of traditional clock trees
Solution Approach 2:
Each IP block is equipped with its own independent clock reference and timing control mechanisms. The blocks autonomously manage their own timing requirements through the Chronos Link protocol, eliminating the need for centralized clock distribution and manual timing closure intervention
2Measurement precision
If manual intervention is used for clock alignment and timing closure in conventional ASIC design, then timing precision is improved, but labor intensity and design time increase significantly
Solution Approach 1:
The Chronos Link protocol enables interfaces to autonomously manage their own timing and synchronization requirements. Each interface independently handles clock alignment and timing closure through built-in protocol mechanisms, completely eliminating manual intervention while maintaining precise timing control
Solution Approach 2:
The Chronos Link protocol provides universal timing and synchronization capabilities across all interfaces. The same protocol layer handles clock alignment, timing closure, and synchronization for all IP blocks uniformly, replacing multiple manual processes with a single automated protocol
3Reliability
If numerous buffers are inserted for clock signal distribution to achieve timing closure, then clock skew is reduced, but device complexity and power consumption increase
Solution Approach 1:
The patent removes the entire buffer-based clock distribution infrastructure by extracting the clock tree synthesis step. Independent clock references at each interface eliminate the need for buffers, achieving clock skew control without adding device complexity
Solution Approach 2:
The Chronos Link protocol acts as an intermediary layer that manages timing and synchronization between interfaces with independent clock references. The protocol handles clock skew compensation through software/firmware mechanisms rather than hardware buffers, reducing overall system complexity
4Ease of manufacture
If traditional links are used between IP blocks, then simple interface connectivity is achieved, but overhead and power consumption increase
Solution Approach 1:
The Chronos Link protocol changes the operational parameters of interface communication by introducing temporal compression and efficient data encoding. This reduces the overhead associated with traditional links while maintaining connectivity, leading to lower power consumption without sacrificing ease of manufacture
Data Source
AI summary
Systems and methods for application specific integrated circuit design using Chronos Links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure.