Chronos Links ASIC Interconnect Protocol for Timing Closure
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Solution Overview
Problem
Conventional ASIC design methods face challenges in achieving balanced clock signal distribution and timing closure, which are labor-intensive and power-consuming, especially due to systematic and random variations from process, voltage, and temperature (PVT) factors, requiring significant manual intervention and consuming a majority of the power in ASIC designs.
Innovation Solution
The implementation of Chronos Links, which are ASIC on-chip and off-chip interconnect communication protocols that allow seamless communication by indicating availability and readiness, replacing traditional links with gaskets and channel repeaters, enabling simplified floorplanning, placement, clock tree synthesis, and timing closure using a double nature arc abstraction for timing estimates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock tree synthesis with buffers is used to achieve balanced clock distribution, then timing closure is achieved, but power consumption increases significantly and manual intervention is required
Solution Approach 1:
The patent extracts and removes the clock tree synthesis step entirely from the design flow. By using asynchronous communication protocols and handshake mechanisms between IP blocks, the need for a global clock distribution network with buffers is eliminated, thereby removing the primary source of power consumption while maintaining timing closure through alternative means
Solution Approach 2:
The patent replaces the mechanical clock distribution system (physical clock trees and buffers) with an asynchronous control system using handshake signals and timing estimation algorithms. This substitution eliminates the need for power-hungry buffer insertion while achieving the same timing closure objective through software-based timing management
2Reliability
If traditional clock tree synthesis with buffers is used to achieve balanced clock distribution, then timing closure is achieved, but device complexity and manual intervention increase
Solution Approach 1:
The patent implements self-service timing management where the system automatically estimates timing characteristics using double nature arc abstraction and adjusts timing parameters without human intervention. The asynchronous handshake protocols enable IP blocks to self-coordinate their operations, eliminating the need for manual clock tree synthesis and buffer placement
Solution Approach 2:
The patent introduces timing estimation algorithms and double nature arc abstraction as intermediaries between design components. These intermediaries automatically calculate and manage timing relationships, replacing the need for manual intervention in clock tree synthesis and providing automated timing closure through computational methods
3Stability of the object's composition
If buffers are inserted for clock signal distribution, then clock skew is minimized, but the number of components and routing complexity increase
Solution Approach 1:
The patent extracts and removes the buffer insertion mechanism from the clock distribution system. By adopting asynchronous communication, the need for buffered clock signals is eliminated entirely, thereby removing the associated routing complexity and component count while maintaining clock synchronization through handshake protocols
Solution Approach 2:
The patent inverts the traditional approach by not distributing a global clock signal at all. Instead of pushing clock signals out to all IP blocks (which requires buffers and complex routing), the system allows each IP block to operate independently and synchronize through incoming handshake signals, effectively inverting the clock distribution paradigm
Data Source
AI summary
Systems and methods for application specific integrated circuit design using Chronos Links are disclosed. A Chronos Link is an ASIC on-chip and off-chip interconnect communication protocol that allows interfaces to transmit and receive information. The protocol may utilize messages or signals to indicate the availability and/or readiness of information to be exchanged between a producer and a consumer allowing the communication to be placed on hold and to be resumed seamlessly. A method includes inserting gaskets and channel repeaters connected to interfaces of multiple intellectual property (IP) blocks in order to replace traditional links with Chronos Links; performing simplified floorplanning; performing simplified placement; performing simplified clock tree synthesis (CTS) and routing; and performing simplified timing closure, where timing estimates are based on a double nature arc abstraction.