Memory Device Chunk Sensing for Accurate Program Verification
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices lack the capability to accurately count the number of memory cells that are not completely programmed during program verification, limiting the effectiveness of program verification processes.
Innovation Solution
A memory device with a sensing circuit that performs operations in units of chunks, each including two or more page buffers, and outputs a final verification result based on the sensing results of these chunks, using a verification result output circuit and control logic to manage the sensing and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If program verification checks all memory cells connected to a selected page, then verification completeness is improved, but the ability to count partially programmed cells is lost
Solution Approach 1:
The patent divides the page buffer array into multiple chunks, where each chunk contains a subset of page buffers. The sensing circuit processes verification results in these segmented chunks rather than handling all page buffers uniformly, enabling precise counting of partially programmed cells while maintaining manageable system complexity
Solution Approach 2:
The patent introduces a hierarchical verification structure with multiple dimensions: page buffer level, chunk level, and final verification level. This dimensional approach allows the system to track verification status at different granularities, enabling accurate counting of partially programmed cells across the entire page
2Measurement precision
If sensing operation processes all page buffers individually, then verification detail is improved, but processing time increases
Solution Approach 1:
The patent segments the sensing operation into chunk-based processing units, where multiple page buffers are processed simultaneously in parallel chunks. This segmentation enables detailed verification of individual cells while reducing overall processing time through parallelization
Solution Approach 2:
The patent merges multiple page buffer verification results into chunk-level results, which are then combined to produce the final verification outcome. This merging approach maintains the detail of individual cell verification while optimizing the overall process throughput
3Reliability
If verification result requires all chunk groups to pass, then verification strictness is improved, but acceptable failure rate increases
Solution Approach 1:
The patent implements a verification standard where at least one chunk group needs to pass for the final verification to succeed. This partial action approach maintains reasonable reliability by catching significant programming failures while allowing minor isolated failures, thereby improving overall programming efficiency
Data Source
AI summary
A memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells; a sensing circuit connected to the plurality of page buffers respectively, the sensing circuit: performing a sensing operation on the page buffers in units of a plurality of chunks, each chunk including two or more page buffers, among the plurality of page buffers, and outputting a sensing result of each of the plurality of chunks; a verification result output circuit for outputting a final verification result of a target program state, among a plurality of program states to which the memory cells are to be programmed, based on the sensing results of the plurality of chunks; and a control logic for controlling the sensing circuit and the peripheral circuit, based on the final verification result.