Conductor-Insulator-Conductor Capacitor Sidewall Encapsulation

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Solution Overview

Problem

In integrated circuits, capacitors with single-crystalline silicon or polysilicon electrodes face instability due to depletion regions when a bias voltage is applied, leading to unpredictable capacitance, and existing MIM capacitors have limitations in capacitance density as semiconductor devices shrink and integrate more densely.

Innovation Solution

A conductor-insulator-conductor capacitor design with a stepped structure and multiple conductive and insulating layers, where the outer electrode surrounds and encapsulates the inner electrode, enhancing capacitance density by increasing the area of the conductive layers and using high-k materials for the insulating layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If single-crystalline silicon or polysilicon electrodes are used in capacitors, then the capacitor can be integrated with existing semiconductor processes, but a depletion region forms when bias voltage is applied causing unstable capacitance

Engineering Contradiction:
Improveintegration with existing processesVSAvoidcapacitance stability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the material parameter of the electrode from single-crystalline silicon or polysilicon to metal or metal alloy, which fundamentally alters the electrical characteristics to eliminate depletion region formation while maintaining compatibility with existing semiconductor manufacturing processes

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs metal or metal alloy materials for the electrode, representing a composite material approach that combines conductivity with stability properties superior to traditional semiconductor materials, thereby achieving both ease of manufacture and reliability

Inventive Principle:
Principle #40Composite materials

2Reliability

If MIM capacitor structure is used, then voltage coefficient of capacitance and temperature coefficient of capacitance are reduced, but capacitance density is limited as device dimensions shrink

Engineering Contradiction:
Improvevoltage and temperature coefficientVSAvoidcapacitance density
Core Design Contradiction:
ReliabilityVSArea of moving object

Solution Approach 1:

The patent transitions from planar capacitor geometry to a three-dimensional structure where the electrode extends along the sidewall of the insulating layer, utilizing vertical space to increase capacitance density without expanding the horizontal footprint

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The electrode is positioned to surround and encapsulate the insulating layer, creating a nested configuration where the conductor wraps around the dielectric, maximizing the interfacial area for capacitance while maintaining a compact overall structure

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design stabilizes capacitance and significantly increases capacitance density, potentially up to 40 to 60 fF/um2, while improving plug landing flexibility and conductivity between electrodes, addressing the limitations of existing capacitors in integrated circuits.

Implementation Method 1

an intermediate dielectric layer located between the inner electrode and the outer electrode and surrounding the inner electrode, such that the inner electrode is electrically isolated from the outer electrode

Methodology Applied
Scientific EffectDielectric isolation: Dielectric

Implementation Method 2

conductor-insulator-conductor capacitor with a higher capacitance density

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS10319521B2Conductor-insulator-conductor capacitor and method of fabricating the same
Publication Date: 2019.06.11 UNITED MICROELECTRONICS CORP
  • US10319521B2 patent drawing
  • US10319521B2 patent drawing
  • US10319521B2 patent drawing

AI summary

A conductor-insulator-conductor capacitor and a method of fabricating the same are provided. The conductor-insulator-conductor capacitor includes first to third conductive layers and first and second insulating layers. The first insulating layer is located on the first conductive layer and covers the first conductive layer. The second conductive layer is located on the first insulating layer and covers at least a portion of the first insulating layer. The second insulating layer is located on the second conductive layer and covers the top surface and the sidewall of the second conductive layer. The second conductive layer is surrounded and encapsulated by the first insulating layer and the second insulating layer. The third conductive layer is located on the second insulating layer and covers the sidewalls of the second insulating layer and the first conductive layer. The third conductive layer is in physical contact with and electrically connected to the first conductive layer.