CIC Filter Coefficient Switching to Reduce Die Area

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Solution Overview

Problem

Existing cascaded integrator comb (CIC) filters, particularly Hogenauer's design, occupy a significant die area in integrated circuits without providing any functional advantage.

Innovation Solution

Implementing a CIC filter using a novel electronic configuration based on equations (3) and (4) that derive coefficients from counter signals, employing phase delay and polarity switching to reduce the number of required circuit instances, thereby minimizing die size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If Hogenauer's CIC filter design is used, then the filter provides complete functionality, but the die area occupied is significant

Engineering Contradiction:
Improvedie areaVSAvoidfilter functionality
Core Design Contradiction:
Area of stationary objectVSAdaptability or versatility

Solution Approach 1:

The patent combines multiple CIC filter stages into a single integrated circuit structure with shared components. The filter merges the functionality of multiple integrator and comb stages while using a common coefficient generator and control logic, thereby reducing the overall die area compared to implementing separate Hogenauer CIC filter blocks for each stage

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The coefficient generator circuit is designed to universally support different oversampling ratios (OSR) and filter orders. The same hardware structure can be configured for various CIC filter specifications through programmable parameters, eliminating the need for dedicated Hogenauer CIC filter instances for each configuration and thus reducing die area

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If the number of circuit instances is reduced, then the die size decreases, but the filter functionality may be compromised

Engineering Contradiction:
Improvedie sizeVSAvoidfilter functionality
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent employs dynamic coefficient updating mechanisms where the coefficient generator can adaptively adjust filter coefficients based on the input signal characteristics and desired filter response. This dynamic adaptation allows the reduced number of circuit instances to maintain equivalent filtering performance to full Hogenauer CIC filters by optimizing coefficients in real-time

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The filter implements parameter change capability through programmable oversampling ratio (OSR) and coefficient values. By changing these parameters, the same hardware structure can achieve different filter responses equivalent to multiple Hogenauer CIC filter configurations, maintaining functionality while reducing die size

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250323629A1Electronic filter
Publication Date: 2025.10.16 NXP USA INC
  • US20250323629A1 patent drawing
  • US20250323629A1 patent drawing
  • US20250323629A1 patent drawing

AI summary

An electronic filter comprising: a first coefficient circuit to provide a first coefficient-signal (coeff0) by applying coeff0=2*OSR−1−counter0, where OSR is the oversampling ratio, when a first counter-signal (counter0)>=OSR and applying coeff0=counter0+1, when counter0<OSR. The filter also comprises a first summation circuit to provide a first polarity-signal, polarity0, as either: coeff0 if the ADC bitstream signal is positive; or −coeff0 if the ADC bitstream signal is negative; and integrate polarity0. The filter also comprises a counter modifier circuit to provide a second counter-signal, derived from counter0; a second coefficient circuit to provide a second coefficient-signal; and a second summation circuit to provide a second sub-filter signal. The filter also comprises an output logic circuit to provide a filter output signal to the filter output terminal, by switching between providing the first sub-filter signal and the second sub-filter signal as the filter output signal, at the frequency of a clock-signal.