CiFET Transistor Structure for Low-Power Analog CMOS
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Analog circuits in ultra-deep submicron CMOS technology face challenges in achieving high-performance integrated circuits with reduced power consumption, compact footprint, and higher operational frequencies due to parasitic issues and the lack of scalable design that is process parameter tolerant, consumes low power, and operates at voltages below 1 volt.
Innovation Solution
A compound device structure utilizing a complementary current field-effect transistor (CiFET) with a common gate and complementary pair of stacked transistors, enabling sub-threshold like operation for analog CMOS circuit designs, providing current input to voltage output trans-impedance functionality and facilitating scalable, low-power, and high-precision analog signal processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional analog circuit components are used in ultra-deep submicron CMOS, then circuit functionality is achieved, but parasitic effects increase and process parameter tolerance decreases
Solution Approach 1:
The patent changes the operating parameters of MOS transistors by utilizing sub-threshold operation and super-saturated source channel conditions, enabling analog circuits to achieve high gain and linearity while maintaining tolerance to process variations in ultra-deep submicron CMOS technologies
Solution Approach 2:
The patent employs composite device structures combining n-type and p-type MOS transistors in complementary configurations, creating CiFET devices that leverage the advantageous properties of both transistor types to reduce parasitic effects and improve process parameter tolerance
2Speed
If analog circuits are designed for high performance, then operational frequency increases, but power consumption increases
Solution Approach 1:
The patent implements dynamic biasing schemes where the operating point of the analog circuits is optimized to achieve high operational frequencies only when needed, allowing the circuit to operate in low-power modes during steady-state conditions while maintaining high-speed capability during signal transitions
Solution Approach 2:
The patent utilizes variable operating parameters including sub-threshold voltage operation and adjustable gate biases to dynamically control the trade-off between operational frequency and power consumption, enabling high-speed operation with minimal power dissipation
3Use of energy by moving object
If analog circuits are designed for reduced power consumption, then power efficiency improves, but operational voltage decreases below 1 volt
Solution Approach 1:
The patent employs parameter changes by operating MOS transistors in sub-threshold regions and utilizing super-saturated source channels, which enable the circuit to maintain analog functionality at operational voltages below 1 volt while achieving reduced power consumption through exponential current-voltage characteristics
4Productivity
If conventional amplifier designs are used, then analog signal processing is achieved, but device area increases
Solution Approach 1:
The patent merges multiple transistor functions into compact CiFET device structures where n-type and p-type transistors are combined in stacked configurations, enabling analog signal processing functions to be achieved in a smaller device footprint by eliminating the need for separate amplifier stages and passive components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The CiFET structure enables high precision, speed, linearity, low noise, and compact physical layout, allowing for integrated analog signal processing at logic speed, overcoming the limitations of conventional analog amplifier designs and enabling continuation of microprocessor capability according to Moore's law.
Implementation Method 1
enabling sub-threshold like operation for analog CMOS circuit designs, providing current input to voltage output trans-impedance functionality
Data Source
AI summary
The present invention relates to a novel and inventive compound device structure, enabling a charge-based approach that takes advantage of sub-threshold operation, for designing analog CMOS circuits. In particular, the present invention relates to a solid state device based on a complementary pair of n-type and p-type current field-effect transistors, each of which has two control ports, namely a low impedance port and gate control port, while a conventional solid state device has one control port, namely gate control port. This novel solid state device provides various improvement over the conventional devices.