Compute-in-Memory Accumulator With Bit-Serial MAC in SRAM
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Solution Overview
Problem
Current compute-in-memory systems face bottlenecks in performance and energy consumption due to the need for extensive data transfer between processor and memory, especially in deep neural networks, where large datasets require impractical cache storage and result in high data movement costs.
Innovation Solution
A compute-in-memory device with a memory array and a bit-serial multiply-accumulate (MAC) circuit that performs operations locally within memory, using SRAM cells and logic gates to multiply and accumulate input signals with weight signals from memory cells, starting from the most significant bit, reducing the need for data transfer and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data is transferred between processor and memory for computation, then computation can be performed using conventional architectures, but data movement time and energy consumption increase significantly
Solution Approach 1:
The patent combines memory storage and computation functions into a single integrated structure. Memory cells store data and simultaneously perform multiply-accumulate operations within the memory array, eliminating the need for separate data transfer between processor and memory. This merging of storage and computation directly reduces energy consumption from data movement while maintaining high computation throughput.
Solution Approach 2:
The patent introduces sense amplifiers and column decode circuits as intermediary components that enable computation to occur within the memory array itself. These intermediaries facilitate local MAC operations by providing the necessary signal amplification and decoding functions within the memory structure, allowing computation to happen at the memory location rather than requiring data movement to external processors.
2Quantity of substance
If cache storage is increased to store large datasets for deep neural networks, then more data can be processed, but the physical space and cost become impractical
Solution Approach 1:
The patent merges the functions of cache memory and computation units into a single integrated memory array. By performing MAC operations directly within the memory cells, the system eliminates the need for separate large-capacity cache structures, achieving both high data storage capacity and computational functionality within the same physical footprint.
Solution Approach 2:
The memory array serves multiple functions simultaneously: it stores weight values, stores input data, and performs computation operations. This multi-functionality allows the same physical memory structure to handle both storage and processing requirements for large neural network datasets, effectively increasing usable data capacity without proportionally increasing physical area.
3Measurement precision
If conventional MAC operations are used with extensive shifting circuits, then full precision computation can be achieved, but device complexity and area increase
Solution Approach 1:
The patent extracts the shifting operation from separate external circuits and integrates it directly into the memory cell structure. By embedding the shifting function within the memory array itself, the system eliminates complex external shifting circuits while maintaining computation precision through localized bit manipulation during MAC operations.
Solution Approach 2:
The memory cells perform their own shifting operations internally during MAC computation without requiring external shifting circuits. Each memory cell autonomously handles the bit manipulation and accumulation operations, reducing overall device complexity while maintaining precision through self-contained computation units within the memory array.
Data Source
AI summary
A compute-in memory (CIM) device is configured to determine at least one input according to a type of an application and at least one weight according to a training result or a configuration of a user. The CIM device performs a bit-serial multiplication based on the input and the weight, from a most significant bit (MSB) of the input to a least significant bit (LSB) of the input to obtain a result according to a plurality of partial-products. A first partial-sum of a first bit of the input is left shifted one bit and then added with a second partial-product of a second bit of the input to obtain a second partial-sum of the second bit. The second bit is one bit after the first bit, and the result is output by the CIM device.