CIM Memory Array Segmentation for Parallel MAC Accuracy
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Solution Overview
Problem
Existing memory devices face inefficiencies in computing-in-memory (CIM) operations due to high computing workload and manufacturing complexity, particularly when all memory cells in a column are coupled to the same computation circuit, leading to degraded accuracy and parallelism in digital-based CIM macros, and increased area and inefficiency in analog-based CIM macros.
Innovation Solution
The memory array is divided into alternating memory cell groups, each coupled to different computation circuits, allowing simultaneous access to multiple rows of memory cells using a common word line, reducing computing workload and manufacturing complexity, and improving efficiency and accuracy in CIM operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all memory cells in a column are coupled to the same computation circuit, then the device complexity is reduced, but the computing workload per computation circuit increases and accuracy deteriorates
Solution Approach 1:
The memory array is divided into multiple memory cell groups, where each group is coupled to a separate computation circuit. This segmentation distributes the computing workload across multiple circuits, improving accuracy while maintaining manageable device complexity through modular organization.
2Reliability
If memory cells are divided into multiple groups coupled to different computation circuits, then computing workload per circuit is reduced and accuracy improves, but device complexity increases
Solution Approach 1:
Multiple computation circuits are designed with identical or similar architectures, allowing them to perform the same CIM operations independently. This universality simplifies the overall design by repeating a standardized block rather than creating complex heterogeneous circuits, thus improving accuracy without proportionally increasing device complexity.
Solution Approach 2:
The patent introduces a new dimension of parallelism by organizing memory cells and computation circuits in a two-dimensional grid structure, where both row and column dimensions can be independently accessed. This spatial arrangement enables simultaneous operations across multiple circuits, improving accuracy while the regular pattern keeps device complexity manageable.
3Productivity
If a common word line is used to access multiple rows simultaneously, then productivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The memory array is segmented into multiple independently accessible memory cell groups. Each group can be accessed through its own word lines, allowing simultaneous access to multiple groups without requiring complex cross-talk management, thus improving productivity while keeping manufacturing precision requirements manageable.
4Productivity
If memory array is configured for simultaneous multi-row access, then productivity improves, but device complexity increases
Solution Approach 1:
The patent implements a two-dimensional memory array structure with independent row and column addressing. This dimensional organization allows simultaneous access to multiple rows across different memory cell groups through a systematic addressing scheme, improving productivity while the regular geometric pattern keeps device complexity manageable through standardized interconnect patterns.
Data Source
AI summary
A memory device includes a memory array of a plurality of memory cells, and first and second Multiply Accumulate (MAC) circuits. The memory cells include first and second memory cell groups. The first memory cell group includes first rows of memory cells coupled to first bit lines. The second memory cell group includes second rows of memory cells coupled to second bit lines. The first rows of memory cells and the second rows of memory cells are alternately arranged along a column direction of the first bit lines and the second bit lines. The first and second MAC circuits are correspondingly coupled, correspondingly through the first and second bit lines, to the memory cells of the first and second memory cell groups.