Compute-in-Memory Array Using Discrete Voltage Levels for Neural Network Operations
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Solution Overview
Problem
Conventional Compute-in-Memory (CIM) architectures face challenges in achieving low energy consumption and high energy efficiency for neural network operations due to high hardware complexity and power consumption, particularly when processing high-frequency analog signals for multi-bit multiplication and addition, which limits operating frequency and increases area cost.
Innovation Solution
The proposed solution involves expanding the weight of input feature data by using multiple bit cells or different operating voltages to generate a weighted current, allowing for multi-bit multiplication and addition without adjusting the read word line voltage, thereby reducing computation time and hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CIM architectures process high-frequency analog signals for multi-bit multiplication and addition, then computation capability is improved, but hardware complexity and power consumption increase
Solution Approach 1:
The patent segments the analog signal processing into multiple discrete voltage levels (e.g., 0V, Vdd/2, Vdd) that can be statically selected. Instead of continuously varying analog signals, the system divides the voltage range into distinct segments, each representing a specific weight value. This segmentation reduces hardware complexity by eliminating the need for high-frequency analog signal generation and processing circuits.
Solution Approach 2:
The patent introduces dynamic voltage regulation that can switch between different operating voltages based on the required weight values. The voltage regulator dynamically adjusts the bit cell operating voltage to match the desired weight, enabling multi-bit multiplication without complex analog signal processing. This dynamic voltage control simplifies the hardware while maintaining computation capability.
2Speed
If conventional CIM architectures use analog signal processing for multi-bit operations, then computation speed is improved, but power consumption increases
Solution Approach 1:
The patent changes the operating voltage parameter of the bit cells to encode weight information. Instead of using analog signal amplitude variations that consume high power, the system uses discrete voltage levels (0V, Vdd/2, Vdd) that can be maintained with low power consumption. The voltage regulator switches between these predefined voltage levels, significantly reducing power consumption while maintaining fast computation speed.
Solution Approach 2:
The patent pre-establishes multiple voltage regulation modes corresponding to different weight values before computation begins. The voltage regulator is pre-configured with the ability to quickly switch between predefined voltage levels, eliminating the need for real-time analog signal generation during computation. This preliminary preparation reduces both power consumption and computation time.
3Measurement precision
If read word line voltage is adjusted for multi-bit multiplication, then weight representation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent makes the bit cell operating voltage serve multiple functions: it simultaneously provides the bias voltage for memory operation and encodes the weight information for computation. By using the same voltage regulation mechanism for both memory read operations and weight representation, the patent eliminates the need for separate voltage control circuits, reducing device complexity while maintaining weight representation accuracy.
Solution Approach 2:
The patent creates equipotential conditions by using discrete voltage levels that are easily maintainable and stable. The voltage regulator ensures that each bit cell operates at a stable voltage level corresponding to its weight value, simplifying the control circuitry. This equipotential approach reduces voltage control complexity while maintaining precise weight representation.
4Productivity
If multiple bit cells are used to expand weight representation, then multi-bit multiplication capability is improved, but area cost increases
Solution Approach 1:
The patent merges the weight representation function with the existing bit cell structure. Instead of adding separate hardware components for weight encoding, the system utilizes the bit cell's inherent voltage characteristics and control mechanisms to represent weights. This merging approach enables multi-bit multiplication capability without proportionally increasing area cost.
Solution Approach 2:
The patent changes the operating voltage parameter of existing bit cells to encode weight information, rather than adding more bit cells to represent weights. By utilizing the voltage dimension of existing cells for weight representation, the system achieves multi-bit multiplication capability while minimizing area expansion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces computation time and power consumption while maintaining high energy efficiency, enabling faster and more efficient neural network operations by statically processing bit cells and using voltage regulation to provide different operating voltages, thus overcoming the limitations of conventional CIM architectures.
Implementation Method 1
each bit cell BC is operated at an operating voltage VDD... providing different operating voltages VDD1, VDD2, ..., VDDN to the bit cells BC
Data Source
AI summary
A memory array for computing-in-memory (CIM) is disclosed. The memory array for CIM includes a bit cell array, at least one word line and at least one bit line. The bit cell array has a plurality of bit cells, wherein each bit cell is operated at an operating voltage. The at least one word line is electrically connected to the bit cell array, wherein the at least one word line is associated with a first parameter. The at least one bit line is electrically connected to the bit cell array, wherein the bit cells extend along a specific direction, each the at least one bit line has an electrical parameter associated therewith, each the bit cell is associated with a second parameter, a first quantity of the plurality of bit cells of the bit cell array extends along the specific direction, and the memory array determines how an expansion associated with at least one of the first parameter and the second parameter is according to the specific direction.