On-Die CIM Bit-Error Detection With Parity-Based Localization
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Solution Overview
Problem
Existing compute-in-memory (CIM) systems face inefficiencies in bit-error detection and localization, particularly due to the need for off-die data transfer and increased operation cycles, which hinder performance in artificial intelligence (AI) applications.
Innovation Solution
Integrating bit-error detectors and locus-inferable data generators within the same semiconductor die as memory cells and multipliers, allowing for parallel bit-error detection and localization, reducing operation cycles and minimizing off-die data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit-error detection is performed using existing CIM systems, then detection capability is provided, but off-die data transfer is required which increases transfer delays and reduces speed
Solution Approach 1:
The patent integrates the bit-error detector directly into the CIM system die, merging previously separate components (memory cells, multipliers, and error detectors) into a unified on-die architecture. This eliminates the need for off-die data transfer and enables parallel operation of detection and computation functions.
2Reliability
If bit-error detection is performed in existing CIM systems, then error detection is achieved, but increased operation cycles are required which reduces productivity
Solution Approach 1:
The integrated bit-error detector operates in parallel with the computation operations, allowing error detection to occur continuously without interrupting the computational workflow. This eliminates sequential operation cycles and maintains continuous productive action.
3Reliability
If bit-error detection is performed using existing CIM systems, then detection function is provided, but off-die transfer delays occur which increase loss of time
Solution Approach 1:
The patent integrates the bit-error detector directly into the CIM system die, merging previously separate components (memory cells, multipliers, and error detectors) into a unified on-die architecture. This eliminates the need for off-die data transfer and enables parallel operation of detection and computation functions.
4Speed
If bit-error detectors are integrated within the same die, then detection speed is enhanced, but device complexity increases
Solution Approach 1:
The integrated bit-error detector is designed to work seamlessly with the existing CIM architecture, utilizing the same memory cells and data pathways for dual purposes: normal computation and error detection. This multi-functionality approach minimizes additional complexity while maximizing speed benefits.
Data Source
AI summary
A compute-in-memory memory (CIM) system includes: in a first region of a semiconductor die, first components including memory cells correspondingly configured to store single bits, and arrays including multipliers and first bit-error detectors; first ones of the memory cells being arranged in corresponding first arrays and being configured to store first bits; second ones of the memory cells being arranged in corresponding second arrays and being configured to store parity bits corresponding to the first bits; and for first groups each of which including a corresponding one of the first arrays, the second arrays, the multipliers and the first bit-error detectors, the multiplier being configured to perform a multiplication of input bits and corresponding ones of the first bits, and the first bit-error detector being configured to perform a detection of a bit-error in the corresponding first bits based on the corresponding parity bits.