Time-Shared Compute-in-Memory Bitcells With Shared Capacitor
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Solution Overview
Problem
In computation-intensive applications like machine learning, the data movement bottleneck in traditional Von Neumann architecture is addressed by distribute data processing hardware across bitcells in compute-in-memory architectures, but these architectures face challenges in density and latency due to the use of shared capacitors across multiple bitcells.
Innovation Solution
A compute-in-memory bitcell array and method that utilize a shared capacitor across multiple bitcells, with transmission gates controlling the charging of the capacitor based on input and stored bits, allowing for time-sharing of the capacitor to reduce latency and increase density by staggering calculation phases across bitcells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a shared capacitor is used across multiple bitcells to increase density, then device density is improved, but latency increases due to time-sharing requirements
Solution Approach 1:
Multiple bitcells share a common capacitor instead of each bitcell having its own dedicated capacitor. This merging of the capacitor resource across multiple bitcells increases device density by reducing the total capacitor area required in the array.
Solution Approach 2:
The system dynamically time-shares the shared capacitor among multiple bitcells through controlled switching. Each bitcell is activated sequentially to use the shared capacitor, with control logic managing the timing and switching to coordinate access to the shared resource.
2Ease of manufacture
If full-rail charging is implemented on the shared capacitor, then high-voltage reset transistors are eliminated, but leakage current becomes a concern
Solution Approach 1:
The capacitor charging is optimized to achieve full-rail voltage swings (from ground to VDD) during computation operations. This parameter change in voltage swing enables the elimination of high-voltage reset transistors while maintaining computational accuracy through adequate voltage margins.
Solution Approach 2:
The shared capacitor undergoes periodic charging and discharging cycles during time-shared operation. Reset transistors are activated periodically to discharge the capacitor between computational operations, managing leakage accumulation through regular reset cycles rather than requiring high-voltage transistors.
3Area of moving object
If time-sharing is implemented across bitcells to increase density, then device density is improved, but calculation latency increases
Solution Approach 1:
Bitcells are pre-charged and prepared in advance during idle periods when the shared capacitor is not being used by other bitcells. This preliminary preparation reduces the active computation time required when each bitcell gains access to the capacitor, thereby reducing overall latency.
Solution Approach 2:
The time-sharing scheme is designed to minimize idle time and maintain continuous useful computation across the bitcell array. Overlapping preparation and computation phases across different bitcells ensures that the system remains productive throughout the time-sharing cycle, reducing total calculation latency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables full-rail charging and discharging of the shared capacitor, reducing the need for high-voltage reset transistors and minimizing leakage, while increasing density towards traditional SRAM bitcell density through time-sharing, which is beneficial in parallel machine learning operations.
Implementation Method 1
a shared capacitor having a first plate connected to a read bit line
Implementation Method 2
controlling a first pair of transmission gates to drive a second plate of a shared capacitor with a first multiplication signal responsive to a first multiplication of a first input bit with a first stored bit
Implementation Method 3
sampling a first charge of the read bit line while grounding the second plate of the shared capacitor after the first multiplication to provide a first sampled charge of the read bit line
Implementation Method 4
a first pair of cross-coupled inverters having a first output node for a first stored bit
Data Source
AI summary
A compute-in-memory array is provided that includes a set of compute-in-memory bitcells that time share a shared capacitor connected between the set of compute-in-memory bitcells and a read bit line.