Computing-in-Memory Chip Partitioning for Faster Inter-Chip Data Transfer
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Solution Overview
Problem
The von Neumann architecture's separation of memory and processor leads to inefficient data transfer, limiting computing power due to mismatched memory and processor speeds.
Innovation Solution
A computing-in-memory chip architecture that integrates arrays of computing-in-memory cells, a peripheral analog circuit IP core, a digital circuit IP core, and a NAND memory on separate chips, with an interface module for high-speed data transfer and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is frequently transferred between the processor and memory in von Neumann architecture, then the computing system can operate, but the transfer speed limitation significantly reduces the operating speed and performance
Solution Approach 1:
The patent segments the computing-in-memory chip into multiple functional chips: first chips with computing-in-memory cell arrays for computation, second chips with peripheral and digital circuit IP cores for control, and third chips with NAND memory for storage. This segmentation allows each chip to specialize in its function while being communicatively coupled through an interface module, enabling parallel operations and eliminating the sequential bottlenecks of von Neumann architecture.
Solution Approach 2:
The patent merges the computing function and memory storage function into integrated computing-in-memory cell arrays on the first chips. The computing-in-memory cells perform computations directly on stored data without requiring transfer to separate processor units, thereby eliminating the memory-wall bottleneck and achieving high-speed computation and data access simultaneously.
2Productivity
If arrays of computing-in-memory cells are integrated on separate first chips, then computing capability is improved, but communication rate between chips becomes a bottleneck during excessive data computations
Solution Approach 1:
The patent introduces an interface module as an intermediary component that communicatively couples the first chips, second chip, and third chip. This interface module manages data transfer between chips and provides direct access paths, ensuring high-speed communication even when multiple first chips perform excessive data computations. The interface module acts as a mediator that coordinates chip-to-chip communication efficiently.
Solution Approach 2:
The patent creates a multi-dimensional chip architecture where first chips with computing-in-memory arrays are communicatively coupled to second chips with circuit cores and third chips with NAND memory through an interface module. This multi-chip modular architecture adds spatial dimensions to the system, allowing parallel data processing across multiple chips while maintaining high-speed inter-chip communication through the interface module.
3Device complexity
If computing-in-memory cells, peripheral circuits, and NAND memory are integrated on the same chip, then device complexity is reduced, but manufacturing yield and fault detection become more difficult
Solution Approach 1:
The patent segments the computing-in-memory system into functionally independent chips: first chips dedicated to computing-in-memory cell arrays, second chips dedicated to peripheral and digital circuit IP cores, and third chips dedicated to NAND memory. This segmentation isolates different functional blocks onto separate chips, making manufacturing defects and faults easier to detect and diagnose while maintaining overall system functionality. Each chip can be manufactured and tested independently, improving overall manufacturing yield.
Data Source
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AI summary
The present disclosure relates to the technical field of computing-in-memory chips, and in particular, to a computing-in-memory chip architecture, a packaging method for a computing-in-memory chip, and an apparatus. The computing-in-memory chip architecture includes: one or more first chips each integrated with one or more arrays of computing-in-memory cells of a computing-in-memory chip, where the one or more arrays of computing-in-memory cells are used to compute the received data; a second chip integrated with a peripheral analog circuit IP core and a digital circuit IP core of the computing-in-memory chip; a third chip between the one or more first chips and the second chip, which is integrated with a NAND memory; and an interface module configured to communicatively couple the one or more first chips, the second chip, and the third chip, such that the one or more first chips and the second chip have access to data stored in the NAND memory, respectively.