Computing-in-Memory Chip Partitioning for High-Speed DRAM Access

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Solution Overview

Problem

The von Neumann architecture's separation of memory and processor leads to inefficient data transfer, limiting computing power due to mismatched memory and processor speeds.

Innovation Solution

A computing-in-memory chip architecture that integrates arrays of computing-in-memory cells, a peripheral analog circuit IP core, a digital circuit IP core, and dynamic random-access memory (DRAM) on separate chips, with an interface module for high-speed data transfer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If computing-in-memory cells, peripheral analog circuit IP core, and digital circuit IP core are integrated on the same chip, then device complexity decreases, but manufacturing precision and yield become difficult to control

Engineering Contradiction:
Improvechip integration complexityVSAvoidchip manufacturing yield
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent segments the computing-in-memory chip into functionally independent first chips (computing arrays), second chip (peripheral and digital IP cores), and third chip (DRAM). This segmentation allows each chip to be manufactured and tested independently, improving manufacturing precision and yield while maintaining overall system functionality through the defined interface module connections.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4571748A1Computing-in-memory chip architecture, packaging method, and apparatus
Publication Date: 2025.06.18 BEIJING ZHICUN (WITIN) TECH CORP LTD
  • EP4571748A1 patent drawingFigure 1
  • EP4571748A1 patent drawingFigure 2
  • EP4571748A1 patent drawingFigure 3

AI summary

The present disclosure relates to the technical field of computing-in-memory chips, and in particular, to a computing-in-memory chip architecture, a packaging method for a computing-in-memory chip, and an apparatus. The computing-in-memory chip architecture includes: one or more first chips each integrated with one or more arrays of computing-in-memory cells of a computing-in-memory chip, where the one or more arrays of computing-in-memory cells are used to compute the received data; a second chip integrated with a peripheral analog circuit IP core and a digital circuit IP core of the computing-in-memory chip; a third chip between the one or more first chips and the second chip, which is integrated with a dynamic random-access memory (DRAM); and an interface module configured to communicatively couple the one or more first chips, the second chip, and the third chip, such that the one or more first chips and the second chip have access to data stored in the DRAM, respectively.