Computing-In-Memory Chip Packaging With DRAM for Inter-Chip Latency
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Solution Overview
Problem
In computing systems with von Neumann architecture, the mismatch between memory transfer speed and processor operating speed limits computing power, and existing computing-in-memory chips face challenges with high data transfer latency and power consumption due to low communication rates between chips.
Innovation Solution
A computing-in-memory system architecture that includes one or more first chips with arrays of computing-in-memory cells, a second chip with a peripheral analog circuit IP core and a digital circuit IP core, and a third chip with DRAM, all communicatively coupled through an interface module, allowing high-speed data transfer and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is frequently transferred between processor and memory in von Neumann architecture, then computing operations can be performed, but transfer latency limits processor operating speed
Solution Approach 1:
The patent merges memory and computing functions into a single computing-in-memory chip, where memory cells directly perform computational operations on stored data. This eliminates the need for frequent data transfers between separate processor and memory components, thereby resolving the latency bottleneck in von Neumann architecture.
Solution Approach 2:
The patent introduces a high-speed interface module as an intermediary between the computing-in-memory chip and external processors. This interface module accelerates data transfer rates, mediating the communication bottleneck and enabling faster data exchange to support higher processor operating speeds.
2Loss of time
If computing-in-memory chips are used to eliminate data transfer between memory and processor, then transfer latency is reduced, but communication rate between chips becomes a new bottleneck
Solution Approach 1:
The interface module serves as a high-speed communication intermediary that bridges the computing-in-memory chip and external systems. It implements specialized communication protocols and signal processing to maximize data transfer rates, ensuring that inter-chip communication does not become a performance bottleneck.
Solution Approach 2:
The patent optimizes communication parameters including signal voltage levels, clock frequencies, and data encoding schemes to achieve maximum communication rates. By adjusting these parameters, the system achieves high-speed data transfer while maintaining signal integrity across the chip interface.
3Adaptability or versatility
If multiple chips are used to implement computing-in-memory system, then functionality is improved, but power consumption increases due to inter-chip communication
Solution Approach 1:
The low-power interface module acts as an energy-efficient intermediary for inter-chip communication. It implements power management features including dynamic voltage scaling, clock gating, and selective activation of communication channels to minimize power consumption while maintaining necessary system functionality.
Solution Approach 2:
The system dynamically adjusts communication parameters such as data transfer rates and voltage levels based on operational requirements. During low-activity periods, communication rates are reduced and voltages are lowered to minimize power consumption, while maintaining full functionality when needed.
Data Source
AI summary
A computing-in-memory system, a packaging method for a computing-in-memory system, and an apparatus are provided. The computing-in-memory system includes: one or more first chips that each include one or more arrays of computing-in-memory cells, where the one or more arrays of computing-in-memory cells are configured to perform computations on received data; a second chip that includes a peripheral analog circuit IP core and a digital circuit IP core; a third chip between the one or more first chips and the second chip, the third chip including dynamic random-access memory (DRAM); and an interface module configured to communicatively couple the one or more first chips, the second chip, and the third chip, such that the one or more first chips and the second chip have access to data stored in the DRAM.