Computing-in-Memory Chip Architecture Resolving Von Neumann Bottleneck
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Solution Overview
Problem
The existing computing systems based on the von Neumann architecture face limitations due to the mismatch between memory transfer speed and processor operating speed, leading to reduced computing power and increased power consumption.
Innovation Solution
The implementation of a computing-in-memory chip architecture that integrates computing units with computing-in-memory cells, peripheral analog circuit IP cores, and digital circuit IP cores on separate chips, with an interface module for efficient communication between them, utilizing different process nodes for each type of core to optimize performance and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is frequently transferred between the processor and memory in von Neumann architecture, then the system can execute instructions, but the computing power is limited due to transfer speed mismatch
Solution Approach 1:
The patent combines memory and computing units into a single computing-in-memory chip, merging previously separate memory and processor functions. This integration eliminates the need for frequent data transfers between separate memory and processor components, directly resolving the speed mismatch limitation while maintaining full computing capability.
2Productivity
If data transfer between processor and memory is increased to match processor operating speed, then computing power improves, but power consumption increases
Solution Approach 1:
By merging memory and computing units into a single chip, the patent eliminates extensive data transfers between separate components. This integration maintains high computing power while significantly reducing power consumption by removing the energy overhead associated with frequent inter-component data transfers.
3Loss of time
If computing units and memory are integrated on the same chip, then data transfer latency is reduced, but device complexity increases
Solution Approach 1:
The patent integrates computing units and memory on the same chip using a unified architecture where computing units directly access memory cells through shared bit lines and word lines. This merging approach minimizes data transfer latency by eliminating external interfaces and inter-chip connections, while the standardized cell structure keeps implementation complexity manageable.
4Ease of manufacture
If separate chips are used for computing units and memory, then manufacturing is simpler, but production costs and reduced yield
Solution Approach 1:
The patent combines computing units and memory on a single chip using compatible manufacturing processes for both components. This integration enables simultaneous fabrication of all chip components in one manufacturing run, improving production yield by eliminating the need for separate chip fabrication and assembly steps, while maintaining ease of manufacture through standardized processes.
Data Source
AI summary
A computing-in-memory system is provided, which includes: one or more first chips each integrated with one or more arrays of computing-in-memory cells of the computing-in-memory system that are configured to perform computations on received data; a second chip, on a first side of which a peripheral analog circuit IP core and a digital circuit IP core of the computing-in-memory system are integrated; and an interface module configured to communicatively couple the second chip to each first chip. The interface module includes one or more first sub-interface modules on each first chip and aligned with each other, and one or more second sub-interface modules integrated on a second side, opposite to the first side, of the second chip and aligned with the one or more first sub-interface modules. A communication path between the second chip and each first chip is integrated on the second side of the second chip.