Compute-In-Memory Column Repair Using Zeroed Redundancy Inputs
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Solution Overview
Problem
Conventional column redundancy repair schemes for compute-in-memory and near-memory-computing devices require significant additional circuitry, increasing space and slowing down processing time due to the need for additional operations.
Innovation Solution
A compute-in-memory device with control circuits that manage input and redundancy data elements, multiplier circuits, and redundancy multiplier circuits to handle defective columns by providing zero values to redundancy multiplier circuits, allowing for efficient column redundancy repair without additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional column redundancy repair schemes are implemented, then defective columns can be repaired, but additional circuitry is required which increases space and slows down processing time
Solution Approach 1:
The patent makes the redundancy multiplier circuits universally applicable by enabling them to perform both normal multiplication operations and redundancy repair operations. The same circuitry that would normally process input data elements is repurposed to process substituted input data elements when column defects are detected, eliminating the need for separate dedicated repair circuitry.
Solution Approach 2:
The patent introduces dynamic reconfiguration capability where the system can switch between normal operation mode and redundancy repair mode based on defect detection. The control circuits dynamically substitute input data elements and reroute operations to redundancy multiplier circuits when defective columns are identified, allowing the system to adapt its behavior without hardware changes.
2Reliability
If conventional column redundancy repair schemes are implemented, then defective columns can be repaired, but processing time increases due to additional operations
Solution Approach 1:
The patent performs preliminary substitution of input data elements with zero values or alternative data elements before the multiplication operation occurs. By pre-processing the input data elements and identifying defective columns in advance, the system avoids time-consuming defect detection and repair operations during the actual computation phase, maintaining processing speed.
Solution Approach 2:
The patent ensures continuous useful action by maintaining the same operational flow and computation pipeline whether in normal mode or redundancy repair mode. The substitution of input data elements and rerouting to redundancy multiplier circuits occurs seamlessly without interrupting the overall computation workflow, preventing time losses associated with mode switching.
3Reliability
If redundancy multiplier circuits are used for defective columns, then repair is achieved, but additional circuitry increases device complexity
Solution Approach 1:
The patent designs redundancy multiplier circuits that can serve dual purposes: processing normal computation tasks and handling redundancy repair operations. The same physical circuits are used for both functions depending on the operational mode, maximizing resource utilization and minimizing the need for additional dedicated repair circuitry.
Solution Approach 2:
The system performs self-service by using its own existing redundancy multiplier circuits to repair defective columns without requiring external or additional repair mechanisms. The control circuits autonomously detect defects, substitute input data elements, and route operations to appropriate redundancy circuits, enabling the system to repair itself using built-in resources.
Data Source
AI summary
A compute-in-memory (CIM) device is provided. The CIM device includes control circuits providing N input data elements and M redundancy input data elements, N and M being greater than zero, multiplier circuits configured to (i) multiply N input data elements by N stored data elements and (ii) provide a multiplier output, and redundancy multiplier circuits configured to (i) multiply the M redundancy input data elements by M stored redundant data elements and (ii) provide a redundancy multiplier output, wherein the control circuits provide (i) the N input data elements to the multiplier circuits and (ii) the M redundancy input data elements with a value of zero to the redundancy multiplier circuits, such that the redundancy multiplier circuits provide a redundancy multiplier output of zero, regardless of a value of the M stored redundant data elements.