CiM Control Circuit for Grouped Word-Line MAC Input
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Solution Overview
Problem
Existing computing-in-memory (CiM) systems face inefficiencies in performing multiplication accumulation (MAC) operations due to the need for bit-by-bit inputting of signals to word lines, leading to increased input cycles and power consumption.
Innovation Solution
A control circuit is employed to select input signals with the same value and transform them into single-bit driving signals, reducing the number of input cycles and activating only a predetermined number of word lines in each period, with a readout circuit calibrating the MAC results using flag signals and multipliers to restore accurate values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If bit-by-bit input signals are provided to word lines for MAC operations, then input precision is maintained, but input cycles and power consumption increase
Solution Approach 1:
The patent merges multiple bit-by-bit input operations into a single parallel input operation by grouping word lines that receive the same input signal. Multiple word lines are activated simultaneously with a single input signal, combining what would otherwise require multiple sequential operations into one concurrent operation, thereby reducing total input cycles while maintaining computational accuracy.
2Measurement precision
If bit-by-bit input signals are provided to word lines for MAC operations, then input precision is maintained, but power consumption increases
Solution Approach 1:
The patent merges multiple bit-by-bit input operations into a single parallel input operation by grouping word lines that receive the same input signal. Multiple word lines are activated simultaneously with a single input signal, combining what would otherwise require multiple sequential operations into one concurrent operation, thereby reducing total power consumption while maintaining computational accuracy.
3Reliability
If all word lines are activated in each period for MAC operations, then computation completeness is ensured, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the set of word lines into multiple groups based on their input signal requirements. Each group is activated in different time periods rather than all word lines being activated simultaneously. This segmentation allows the system to maintain computation completeness while reducing the number of active word lines in each period, thereby lowering power consumption and control complexity.
Solution Approach 2:
The patent implements periodic activation of different word line groups across multiple time periods. Instead of activating all word lines continuously, the system uses periodic action to activate specific groups at specific times, ensuring that all necessary computations are completed over the course of multiple periods while reducing instantaneous device complexity and power requirements.
4Reliability
If all word lines are activated in each period for MAC operations, then computation completeness is ensured, but power consumption increases
Solution Approach 1:
The patent segments the set of word lines into multiple groups based on their input signal requirements. Each group is activated in different time periods rather than all word lines being activated simultaneously. This segmentation allows the system to maintain computation completeness while reducing the number of active word lines in each period, thereby lowering power consumption and control complexity.
Solution Approach 2:
The patent implements periodic activation of different word line groups across multiple time periods. Instead of activating all word lines continuously, the system uses periodic action to activate specific groups at specific times, ensuring that all necessary computations are completed over the course of multiple periods while reducing instantaneous power consumption.
Data Source
AI summary
Control circuits, memory systems, and operating methods are provided. A control circuit is configured to control operations of a memory array. The control circuit comprises an input circuit and a readout circuit. The input circuit is configured to: receive a plurality of input signals respectively driving a plurality of word lines of the memory array; select at least one first input signals having a first input value; and provide an activating voltage to at least one first word lines corresponding to the at least one first input signals in a first period. The readout circuit is coupled to a plurality of bit lines of the memory array, and configured to calculate a plurality of output sum signals according to the first input value.