CIM Memory Macro With Dual Bit Lines for Concurrent Weight Updates

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Solution Overview

Problem

Existing approaches to computing-in-memory (CIM) operations require stopping CIM operations whenever weight data updating is performed, leading to issues such as lowered performance, increased processing time, and higher power consumption due to the need for external weight buffers.

Innovation Solution

Incorporating weight buffers within the same memory macro as the memory array, allowing simultaneous performance of weight data updating and CIM operations, thereby eliminating or reducing the need for external weight buffers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If weight data updating is performed using external weight buffers, then weight data can be updated, but CIM operations must be stopped leading to lowered performance and increased processing time

Engineering Contradiction:
Improveweight data updating capabilityVSAvoidCIM operation performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges the weight buffer functionality directly into the memory macro structure, combining the weight storage function with the memory array. This integration allows the memory device to simultaneously perform weight data updating and CIM operations without requiring external weight buffers, thereby resolving the contradiction between weight data updating capability and CIM operation performance.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The memory macro is designed to serve multiple functions: it can perform both weight data updating operations and CIM operations simultaneously. This multi-functionality eliminates the need to stop CIM operations during weight data updating, as the same memory infrastructure handles both tasks concurrently, improving overall productivity while maintaining reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If external weight buffers are used for weight data updating, then weight data can be updated, but chip area and manufacturing costs increase

Engineering Contradiction:
Improveweight data updating capabilityVSAvoidchip area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines the weight buffer functionality with the memory array within the same memory macro, eliminating the need for separate external weight buffers. This merging reduces the overall chip area required while maintaining the capability to update weight data, as the same memory infrastructure serves dual purposes.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If external weight buffers are used for weight data updating, then weight data can be updated, but power consumption increases due to back-and-forth data movement

Engineering Contradiction:
Improveweight data updating capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent merges weight buffer and memory array functions within the same memory macro, eliminating the need for data to move back and forth between external weight buffers and the memory array. This integration significantly reduces power consumption by minimizing data movement while maintaining full weight data updating capability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20250342870A1Method for computing-in-memory (CIM)
Publication Date: 2025.11.06 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250342870A1 patent drawing
  • US20250342870A1 patent drawing
  • US20250342870A1 patent drawing

AI summary

A method of operating a memory device includes storing weight data in at least one memory segment of a memory array, holding new weight data to be updated in the at least one memory segment in at least one weight buffer coupled to the at least one memory segment, reading the weight data from the at least one memory segment through a first bit line, generating output data corresponding to a computation performed on input data and the weight data read from the at least one memory segment, receiving the new weight data held in the at least one weight buffer through a second bit line different from the first bit line, and writing the received new weight data to the at least one memory segment.