Compute-In-Memory GRAND Decoding for Low-Latency Channel Codes

The patent replaces conventional logic gate-based computing with compute-in-memory technology, where memory cells directly perform computational operations. This substitution eliminates the need for separate logic gates and interconnections, significantly reducing device complexity while maintaining the codebook membership checking capability. The memory cells themselves execute the syndrome computation and error pattern evaluation functions that traditionally required complex logic circuits.

The patent merges the storage function and computing function into a single integrated structure. The compute-in-memory device combines memory cells for storing test error pattern syndromes with computing elements that perform concurrent evaluation operations. This merging eliminates the separation between memory and logic units, reducing overall device complexity and overhead while enabling efficient GRAND decoding operations.

The patent implements dynamic parallel evaluation capabilities in the compute-in-memory device, where multiple test error pattern syndromes are evaluated concurrently through programmable computation operations. This dynamic parallelism allows the system to adaptively process multiple error patterns simultaneously without requiring a fixed, overly complex hardware structure, thereby reducing worst-case decoding latency while maintaining manageable device complexity.

The patent segments the decoding process into multiple parallel evaluation streams within the compute-in-memory device. Different test error pattern syndromes are evaluated in parallel through divided computational paths, allowing simultaneous processing of multiple candidates. This segmentation enables high parallelization factors without proportionally increasing overall device complexity, as the compute-in-memory architecture handles multiple operations within its integrated structure.