Floating-Point CIM MAC Padding for Mantissa Alignment Accuracy
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Solution Overview
Problem
Machine learning computations in neural networks face significant bottlenecks due to memory latency and data transfer inefficiencies, particularly when processing large datasets, leading to potential errors and information loss during MAC operations on floating-point numbers.
Innovation Solution
A compute-in-memory (CIM) circuit that determines whether to pad the sum result with non-zero values after shifting, using a padding pattern to minimize information loss and enhance accuracy by aligning mantissa bits with exponent sums, thereby improving the precision of floating-point operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If compute-in-memory (CIM) operations are performed on floating-point numbers without padding, then computation speed is improved, but accuracy deteriorates due to number loss during summation
Solution Approach 1:
The patent applies preliminary action by determining the number of padding bits before the summation operation occurs. The system calculates how many bits need to be padded in the fraction field based on the exponent differences of the input numbers, ensuring that sufficient precision is maintained during the MAC operation. This pre-determined padding strategy prevents accuracy loss without requiring post-computation correction.
Solution Approach 2:
The patent dynamically changes the padding parameter (number of padding bits) based on the specific characteristics of the input floating-point numbers. By adjusting the padding bits according to the exponent differences and the required precision for each specific computation, the system optimizes the balance between computation efficiency and accuracy for different operational scenarios.
2Measurement precision
If padding bits are added to maintain precision, then accuracy is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the CIM circuit to automatically determine and apply the appropriate number of padding bits without external intervention. The system uses the exponent information from the input floating-point numbers to self-calculate the required padding, eliminating the need for complex external control logic and reducing overall device complexity while maintaining high accuracy.
3Measurement precision
If dynamic padding is applied based on exponent differences, then accuracy is improved, but computation time increases
Solution Approach 1:
The patent applies preliminary action by determining the number of padding bits in advance, based on the exponent differences of the input numbers, before the actual multiplication and summation operations. This pre-calculation approach allows the system to prepare the appropriate precision level upfront, avoiding time-consuming adjustments during the computation process and minimizing the impact on overall computation time.
Data Source
AI summary
A computing-in-memory circuit (CIM) circuit includes an input circuit configured to receive: N first inputs and N second inputs; N multiplier circuits, each configured to multiply a corresponding input pair to generate a corresponding one of N products; a shifting circuit configured to align the N products according to a largest exponent sum to generate a corresponding one of N aligned products; an adder circuit configured to sum a respective pair of the N aligned products to generate a sum result; and a padding circuit configured to: (i) determine a padding number based on a bit position of a largest non-zero value in the sum result, (ii) shift the sum result by a number of bits corresponding to the padding number to generate a shifted sum result, and (iii) apply a padding pattern having a length of the padding number to the shifted sum result to generate a padded sum.