CIM MAC Stage Scheduling for Peak Current Reduction

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Solution Overview

Problem

Existing compute-in-memory (CIM) circuits consume high overall peak currents due to simultaneous performance of MAC stages with similar peak currents, leading to supply voltage fluctuations and performance issues.

Innovation Solution

The CIM circuit arranges MAC stages across different computing cells to be performed at different timings based on their peak currents, using a global CIM controller to schedule operations and avoid simultaneous high peak current accumulation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MAC stages with similar peak currents are performed simultaneously across multiple computing cells, then computational throughput is improved, but overall peak current consumption increases causing supply voltage fluctuations

Engineering Contradiction:

Improvecomputational throughputVSAvoidpeak current consumption

Core Design Contradiction:

ProductivityVSPower

Solution Approach 1:

The patent segments the computational workload by dividing MAC stages into different groups based on their peak current characteristics. Computing cells are assigned to different groups, and MAC stages within each group are scheduled at different timings to prevent simultaneous peak current accumulation, thereby resolving the contradiction between throughput and peak current consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic scheduling of MAC stages based on real-time peak current conditions. The system adjusts the timing of MAC stage execution dynamically, allowing flexible coordination between computing cells to balance computational throughput with peak current management, preventing supply voltage fluctuations while maintaining productivity.

Inventive Principle:

Principle #15Dynamics

2Stability of the object's composition

If MAC stages are scheduled at different timings to reduce peak current, then supply voltage stability is improved, but computational throughput may be reduced

Engineering Contradiction:

Improvesupply voltage stabilityVSAvoidcomputational throughput

Core Design Contradiction:

Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent employs periodic scheduling patterns for MAC stages across computing cells. By organizing MAC stage execution into periodic cycles with staggered timings, the system maintains regular computational flow that ensures supply voltage stability while preserving overall computational throughput through structured periodic operation.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The patent ensures continuous computational activity by overlapping MAC stage executions across different computing cells. While individual cells operate at staggered timings to stabilize voltage, the system as a whole maintains continuous useful action through parallel processing in different cell groups, preventing throughput degradation.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20260051343A1Compute-in-memory systems and methods for operating the same

Publication Date: 2026.02.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A circuit includes a first number of computing cells, wherein each of the computing cells comprises a second number of stages which, when collectively performed, are configured to provide at least one MAC result of a respective plurality of input data elements and a respective plurality of weight data elements. The circuit includes a global CIM controller operatively coupled to the computing cells, and is configured to schedule a first one of the stages of a first one of the computing cells and a first one of the stages of a second one of the computing cells to be simultaneously performed, based on identifying that a first peak current previously consumed by the first stage of the first computing cell and a second peak current previously consumed by the first stage of the second computing cell are different.