CIM Memory Read Circuit Using Current DAC and Gated Cell Currents
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Solution Overview
Problem
Conventional compute-in-memory (CIM) circuits face challenges in high-speed operations due to high power consumption and increased manufacturing costs, as they rely on voltage signals and require large static currents, along with the need for clamping circuits to ensure even cell currents.
Innovation Solution
The solution involves computing current signals from a CIM memory circuit by comparing them with reference currents generated by a current digital-to-analog converter (DAC) circuit, using clock-gated switches to produce even currents and reduce static power consumption, and employing a current comparator to generate an output signal indicative of the difference between the two currents, which is then adjusted by a logic circuit to match the memory current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If voltage signals and large static currents are used in conventional CIM circuits, then computing operations can be performed, but power consumption increases and manufacturing costs increase
Solution Approach 1:
The patent replaces voltage-based signal processing with current-based signal processing. Current signals are used throughout the CIM circuit including in the memory cells, switches, and comparator, eliminating the need for voltage-to-current conversions and large static voltage currents. This substitution reduces power consumption while maintaining computing functionality through current-mode operations.
Solution Approach 2:
The patent employs clock-gated switches that operate in periodic cycles rather than continuously. The switches are enabled during specific clock phases to perform computing operations and disabled during other phases to reduce static power consumption. This periodic operation allows the circuit to maintain computing capability when needed while minimizing power draw during non-operational periods.
2Stability of the object's composition
If clamping circuits are added to ensure even cell currents, then current uniformity improves, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent uses self-adjusting current mirrors and feedback mechanisms within the memory cell array that automatically balance cell currents without external clamping circuits. The current-mode operation combined with proportional routing and natural current sharing through matched transistors allows the system to self-regulate current distribution, eliminating the need for additional clamping circuitry while maintaining current uniformity.
3Loss of energy
If clock-gated switches are used to reduce static power consumption, then power efficiency improves, but current evenness may be affected
Solution Approach 1:
The patent incorporates feedback mechanisms where the current comparator continuously monitors the differential current signal and provides feedback to adjust the operation of clock-gated switches. This feedback ensures that even when switches are periodically enabled and disabled, the current distribution remains balanced and even across memory cells, maintaining current uniformity while achieving power reduction through periodic operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-speed (GHz) CIM operations with reduced power consumption and manufacturing costs, as it eliminates the need for clamping circuits and allows for efficient current comparison, facilitating faster and more efficient computing.
Implementation Method 1
A current comparator is used to compare the memory current through the memory circuit and the reference current through the current DAC circuit and generates an output signal indicative of the difference between the two currents
Data Source
AI summary
In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.