CIM Memory Array Layout for Parallel MAC Access and Accuracy
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Solution Overview
Problem
Existing memory devices face inefficiencies in computing-in-memory operations due to high computing workload on computation circuits and limitations in simultaneous access of memory cells, leading to degraded accuracy and parallelism in digital and analog-based systems.
Innovation Solution
A memory array configuration with alternately arranged memory cell groups coupled to different computation circuits, allowing simultaneous access of multiple rows using common word lines, reducing computing workload and improving efficiency, especially in CIM operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If memory cells are arranged in traditional configuration with all cells in each column coupled to the same computation circuit, then the structure is simple, but the computing workload on each computation circuit becomes excessively high and accuracy degrades
Solution Approach 1:
The patent divides the memory array into multiple memory cell groups, where each group contains a subset of memory cells coupled to a dedicated computation circuit. This segmentation distributes the computing workload across multiple circuits, improving computation accuracy by preventing overload while maintaining a structured but not overly complex architecture through systematic organization.
Solution Approach 2:
The patent implements local quality by assigning different computation circuits to different memory cell groups, allowing each computation circuit to operate with optimized parameters and characteristics suited to its specific workload, thereby improving overall computation accuracy without requiring complete redesign of the entire memory system.
2Productivity
If multiple rows of memory cells are accessed simultaneously using separate word lines, then access parallelism is improved, but the number of word lines and device complexity increases
Solution Approach 1:
The patent makes word lines multi-functional by enabling a single word line to simultaneously access multiple rows of memory cells across different memory cell groups. This universality allows the system to achieve high access parallelism without proportionally increasing the number of word lines, as each word line serves multiple purposes and accesses multiple rows concurrently.
Solution Approach 2:
The patent merges the functionality of multiple word lines by allowing a single word line to control access to multiple rows simultaneously. This combining of access functions maintains high productivity through parallel access while reducing the total number of word lines required, thereby avoiding excessive device complexity.
3Productivity
If data is moved between memory and computation circuits through traditional interfaces, then the architecture is simple, but data movement bottlenecks limit computing efficiency
Solution Approach 1:
The patent introduces a new dimension to data movement by implementing direct coupling between memory cell groups and computation circuits, bypassing traditional sequential data movement paths. This dimensional change in the data architecture enables parallel data flow paths, dramatically improving computing efficiency without requiring overly complex intermediary structures.
Solution Approach 2:
The patent introduces computation circuits as intermediaries directly integrated with memory cell groups, creating efficient data movement pathways. These intermediary computation circuits process data locally before it moves to subsequent stages, improving overall computing efficiency while maintaining a manageable architecture through systematic integration rather than chaotic complexity.
Data Source
AI summary
A memory device includes a memory array of a plurality of memory cells, and first and second Multiply Accumulate (MAC) circuits. The memory cells include first and second memory cell groups. The first memory cell group includes first rows of memory cells coupled to first bit lines. The second memory cell group includes second rows of memory cells coupled to second bit lines. The first rows of memory cells and the second rows of memory cells are alternately arranged along a column direction of the first bit lines and the second bit lines. The first bit lines and the second bit lines are alternately arranged along a row direction of the first rows and the second rows. The first and second MAC circuits are correspondingly coupled, correspondingly through the first and second bit lines, to the memory cells of the first and second memory cell groups.