CIM Memory Saturation Detection for Sparse Matrix Multiplication
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Solution Overview
Problem
Existing ANN hardware accelerators, particularly those using analog accelerators, are inefficient in multiplying sparse matrices due to the large size of S/H circuit capacitors and high resolution ADCs, leading to significant power and area costs.
Innovation Solution
Implementing a CIM array module with saturation detection units (SDUs) that use significantly smaller capacitors and ADCs, achieving iso-accuracy performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If S/H circuit capacitors and ADCs are sized to multiply dense matrices, then dense matrix multiplication performance is improved, but power consumption and area increase significantly when multiplying sparse matrices
Solution Approach 1:
The patent implements dynamic capacitor sizing in the S/H circuits, allowing the capacitor size to be adjusted based on the sparsity of the input matrices. The system transitions from static capacitor sizes (optimized for dense matrices) to dynamic capacitor sizes that adapt to the actual computational needs of sparse matrix multiplication, thereby reducing power consumption while maintaining performance.
Solution Approach 2:
The patent changes the parameter of capacitor size based on matrix sparsity characteristics. By detecting the sparsity level and adjusting the capacitor size accordingly, the system optimizes the trade-off between performance and power consumption. This parameter change allows the same hardware to efficiently handle both dense and sparse matrix multiplication scenarios.
2Measurement precision
If S/H circuit capacitors and ADCs are sized for dense matrices, then calculation accuracy for dense matrices is maintained, but hardware area increases for sparse matrix operations
Solution Approach 1:
The patent implements dynamic capacitor sizing that adapts to the sparsity of input matrices. Instead of using a fixed, large capacitor size optimized for dense matrices, the system dynamically adjusts the capacitor size based on the actual computational requirements of sparse matrix operations, thereby reducing hardware area while maintaining calculation accuracy.
Solution Approach 2:
The patent changes the physical parameter of capacitor size based on the sparsity parameter of the input matrices. This parameter change enables the system to use smaller capacitors for sparse matrix operations while maintaining sufficient accuracy, thus reducing the overall hardware area required for the analog accelerator.
3Measurement precision
If high resolution ADCs are used, then measurement precision for dense matrices is improved, but power consumption and area increase for sparse matrix multiplication
Solution Approach 1:
The patent changes the resolution parameter of the ADCs based on the sparsity of the input matrices. For sparse matrix operations, the system uses lower resolution ADCs, while reserving high resolution for dense matrix operations. This dynamic parameter adjustment reduces power consumption and area for sparse matrix multiplication while maintaining high precision when needed.
Data Source
AI summary
A compute-in-memory (CIM) array module and a method for performing dynamic saturation detection for a CIM array are provided. The CIM array module includes a CIM array, saturation detection units (SDUs) and a controller. The CIM array includes selectable row signal lines, column signal lines and cells. Each cell is located at an intersection of a selectable row signal line and a column signal line, and each cell has a programmable conductance. The SDUs are selectively coupled to at least one column signal line, and each SDU is configured to, for each column signal line, generate an analog signal, and identify the column signal line as a saturated column signal line when a voltage of the analog signal is greater than a saturation threshold voltage, or a current of the analog signal is greater than a saturation threshold current.