Compute-in-Memory NVM Array for High-Throughput Analog MAC
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Solution Overview
Problem
Conventional compute-in-memory (CIM) arrays face limitations in MAC result throughput due to large substrate area consumption by integrator and ADC circuits, power consumption in processing positive and negative weight results, and relatively low write/refresh cycle times, which can lead to disturb issues in adjacent memory cells.
Innovation Solution
The proposed CIM device stores sets of multiplier values in memory cell rows, with multiplicand values applied column-wise to generate cell currents or voltages based on stored weight values. These currents are accumulated analogously on dedicated source lines, then multiplexed to an ADC to generate digital MAC values, allowing for efficient MAC operations and neural network computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CIM arrays use integrator and ADC circuits for MAC operations, then MAC results can be generated, but large substrate area is consumed
Solution Approach 1:
The patent extracts the integrator and ADC circuits from the conventional CIM array architecture, eliminating the need for these large substrate area components while maintaining MAC operation functionality through alternative computational approaches using memory cell resistance values directly
Solution Approach 2:
The patent makes the memory cells serve multiple functions: they store data and simultaneously perform computational operations (multiplication and accumulation) through their resistance values, eliminating the need for separate integrator and ADC circuits dedicated to MAC operations
2Measurement precision
If conventional CIM arrays process positive and negative weight results separately, then accurate MAC operations are achieved, but power consumption increases
Solution Approach 1:
The patent merges the processing of positive and negative weight results into a unified computational approach where memory cell resistance values (which can represent signed weights) directly participate in MAC operations without separate processing paths, reducing power consumption while maintaining accuracy
3Productivity
If conventional CIM arrays use standard write/refresh cycle times, then memory operations are performed, but adjacent memory cells experience disturb issues
Solution Approach 1:
The patent applies preliminary anti-action by implementing specific write/refresh cycle timing protocols that prevent disturb issues in adjacent memory cells before they can occur, allowing faster cycle times while maintaining memory cell stability through proactive interference prevention
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances MAC result throughput, reduces power consumption, and improves write/refresh cycle times by optimizing the architecture to handle signed input values efficiently, enabling faster and more accurate neural network operations.
Implementation Method 1
memory cells can generate a cell current or voltage that varies according to the stored weight values
Implementation Method 2
Cell currents or voltages can be summed on source lines to generate analog MAC results
Data Source
AI summary
A method can include, for each row of a nonvolatile memory (NVM) cell array, generating a multiply-accumulate (MAC) result for the row by applying input values on bit lines. Each MAC result comprising a summation of an analog current or voltage that is a function of each input value modified by a corresponding weight value stored by the NVM cells of the row. By operation of at least one multiplexer, one of the rows can be connected to an analog-to-digital converter (ADC) circuit to convert the analog current or voltage of the row into a digital MAC value. A storage element of each NVM cell can be configured to store a weight value that can vary between no less than three different values. Corresponding devices and systems are also disclosed.