Compute-in-Memory Read Wire Encoding for Isolated Voltage Levels
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Solution Overview
Problem
Current semiconductor-based artificial intelligence implementations face inefficiencies due to high computational overhead and energy consumption from frequent data movement between CPU/GPU and system memory in traditional neural network processing.
Innovation Solution
The integration of compute-in-memory (CIM) circuits, which perform mathematical computations near memory cells, reducing data transfer by using multi-level read wires with isolated voltage distributions to enhance processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional CPU/GPU processing with system memory is used, then computational flexibility is maintained, but data movement overhead and energy consumption increase significantly
Solution Approach 1:
The patent merges computation and memory functions into a single integrated structure where memory cells directly perform computational operations. The memory array serves dual purposes: storing data and executing computations, eliminating the need for separate CPU/GPU processing units and reducing data movement between components.
Solution Approach 2:
The memory cells perform computations autonomously using their own stored data without requiring external processing units. The in-memory computation capability allows the memory structure to serve its own computational needs, reducing dependence on separate processing hardware and minimizing data transfer requirements.
2Productivity
If multi-level read wires are used to increase data density, then processing efficiency improves, but voltage distribution isolation becomes challenging
Solution Approach 1:
The patent segments the voltage distribution into isolated levels within the read wire structure. By creating distinct voltage zones that are electrically isolated from each other, the system can maintain multiple voltage levels on the same read wire without interference, enabling multi-level data representation while preserving signal integrity.
Solution Approach 2:
The patent introduces intermediary structures or mechanisms that mediate between different voltage levels on the read wire. These intermediaries provide electrical isolation or buffering between voltage distributions, allowing multi-level signaling while preventing voltage interference and maintaining reliable data reading.
Data Source
AI summary
An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.