Analog Compute-in-Memory Error Mitigation via Redundancy Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current analog compute-in-memory (CiM) architectures face challenges in data reliability due to process, voltage, and temperature uncertainties, with existing error correction codes and redundancy methods being either ineffective or too resource-intensive, and often failing to detect systematic errors.
Innovation Solution
The implementation of in-memory redundancy logic that mimics normal operations with lower overhead, allowing for real-time monitoring of PVT changes and early detection of failures, particularly focusing on the most significant bit flipping, to provide an improved operational guard band and enhance data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction codes and redundancy methods are used in analog CiM architectures, then data reliability may be improved, but resource overhead and complexity increase significantly
Solution Approach 1:
The patent implements self-service by enabling computational nodes to autonomously detect and correct their own errors through built-in monitoring mechanisms. Each computational node includes error detection logic that continuously monitors its own operational status and corrects errors without requiring external intervention or complex system-wide redundancy, thereby improving reliability while minimizing resource overhead.
Solution Approach 2:
The patent applies preliminary action by proactively monitoring computational nodes for errors before they propagate and affect system output. The error detection mechanism continuously checks operational status in advance, allowing early error identification and correction. This preventive approach ensures data reliability is maintained while avoiding the need for extensive post-computation verification resources.
2Reliability
If existing error mitigation methods are implemented, then some errors may be detected, but systematic errors and PVT uncertainties remain undetected
Solution Approach 1:
The patent implements feedback by continuously monitoring computational node status and using this information to detect and correct errors. The system incorporates feedback loops that track operational parameters, compare expected versus actual behavior, and trigger corrective actions when deviations indicate errors. This feedback mechanism enables detection of various error types including systematic errors and PVT uncertainties that traditional methods miss.
Solution Approach 2:
The patent applies universality by designing an error detection mechanism that handles multiple error types through a single integrated approach. The monitoring system is capable of detecting random errors, systematic errors, PVT-related errors, and bit-flip errors using the same fundamental mechanism, thereby providing comprehensive error coverage without requiring separate specialized detection systems for each error type.
3Productivity
If analog CiM operations are performed without error mitigation, then latency and energy consumption are reduced, but data reliability deteriorates
Solution Approach 1:
The patent merges error mitigation functionality directly into the computational nodes themselves, combining computation and error detection in a single integrated structure. By embedding monitoring and correction logic within the computational nodes rather than as separate external components, the system achieves error protection without adding significant latency or energy overhead, thus maintaining computational efficiency while improving reliability.
Data Source
AI summary
A compute-in-memory (CiM) circuit or structure arranged to detect errors. Examples include detecting errors associated with weight bits stored to computational nodes included in a CiM circuit or structure based on use of complimented bit values. Examples also include detecting errors in the CiM circuit or structure based on using at least some computational nodes included in an array of computational nodes to monitor for the errors during generation of computation results by other computational nodes included in the array.